IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
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출원번호 |
US-0860116
(2004-06-02)
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등록번호 |
US-8705579
(2014-04-22)
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발명자
/ 주소 |
- Anderson, Jon James
- Steele, Brian
- Wiley, George Alan
- Shekhar, Shashank
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
2 인용 특허 :
278 |
초록
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A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers
A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.
대표청구항
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1. A state machine for use in obtaining synchronization in an electronic system transferring digital data at a high rate between a host device and a client device over a communication path, the state machine configured to have at least one Acquiring Sync States synchronization states, and at least t
1. A state machine for use in obtaining synchronization in an electronic system transferring digital data at a high rate between a host device and a client device over a communication path, the state machine configured to have at least one Acquiring Sync States synchronization states, and at least two In-Sync States synchronization states, comprising: a circuit to change synchronization states, the synchronization states comprising the at least one Acquiring Sync States synchronization states and at least two In-Sync States synchronization states;the circuit to change synchronization states comprising configuring the circuit for changing from a first Acquiring Sync State to a first In-Sync State comprising a no-sync state transitioning to the first In-Sync State based on detecting a presence of a synchronization pattern and a good CRC at a subframe boundary;the circuit to change synchronization states comprising configuring the circuit for changing from the first In-Sync State to a next In-Sync State comprising detecting the presence of a single bad CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data; andthe circuit to change synchronization states comprising configuring the circuit for changing from the next In-Sync State to the first In-Sync State comprises detecting a presence of a single good CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data. 2. The state machine of claim 1, wherein one condition for changing from a first In-Sync State to the Acquiring Sync State comprises detecting the presence of no synchronization pattern or a bad CRC value at a sub-frame boundary. 3. The state machine of claim 1, wherein one condition for changing between a first In-Sync State or a next In-Sync State, of the at least two In-Sync States, to the Acquiring Sync State comprises detecting the presence of a predetermined number of consecutive bad CRC values. 4. A method for obtaining synchronization in an electronic system transferring digital data at a high rate between a host device and a client device over a communication path, the system configured to have at least one Acquiring Sync States synchronization states, and at least two In-Sync States synchronization states, the method comprising the steps of: changing from a first Acquiring Sync State to a first In-Sync State by transitioning from a no sync state to the first In-Sync State by detecting a presence of a synchronization pattern and a good CRC at a subframe boundary by a processor;changing from the first In-Sync State to a next In-Sync State by detecting the presence of a single bad CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data by the processor; andchanging from the next In-Sync State to the first In-Sync State by detecting a presence of a single good CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data by the processor. 5. The method of claim 4, wherein one condition for changing from a first In-Sync State to the Acquiring Sync State comprises the step of detecting the presence of no synchronization pattern or a bad CRC value at a sub-frame boundary. 6. The method of claim 4, wherein one condition for changing between a first In-Sync State or next In-Sync State, of the at least two In-Sync States, to the Acquiring Sync State comprises the step of detecting the presence of a predetermined number of consecutive bad CRC values. 7. A non-transitory storage media comprising program instructions which are hardware computer-executable to implement synchronization in an electronic system for transferring digital data at a high rate between a host device and a client device over a communication path, the system configured to have at least one Acquiring Sync States synchronization states, and at least two In-Sync States synchronization states, the storage media comprising: program instructions that cause a change from a first Acquiring Sync State to a first In-Sync State by a transition from a no sync state to the first In-Sync State by a detection of a presence of a synchronization pattern and a good CRC at a subframe boundary;program instructions that cause a change from the first In-Sync State to a next In-Sync State by the detection of the presence of a single bad CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data; andprogram instructions that cause a change from the next In-Sync State to the first In-Sync State by the detection of the presence of a single good CRC value without using a synchronization pattern, based on the calculated CRC value for every packet of the transferred digital data. 8. The storage media of claim 7, wherein one condition for changing from a first In-Sync State to the Acquiring Sync State comprises program instructions that cause the detection of the presence of no synchronization pattern or a bad CRC value at the sub-frame boundary. 9. The storage media of claim 7, wherein one condition for changing between a first In-Sync State or next In-Sync State, of the at least two In-Sync States, to the Acquiring Sync State comprises program instructions that cause the detection of the presence of a predetermined number of consecutive bad CRC values.
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