최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
---|---|
국제특허분류(IPC7판) |
|
출원번호 | US-0314435 (2011-12-08) |
등록번호 | US-8709880 (2014-04-29) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 3 인용 특허 : 327 |
A method of manufacturing semiconductor devices: providing a first device including a first die and second die, where the first die is diced from a first wafer, the second die is diced from a second wafer, the first die is connected to the second die using at least one through-silicon-via; providing
A method of manufacturing semiconductor devices: providing a first device including a first die and second die, where the first die is diced from a first wafer, the second die is diced from a second wafer, the first die is connected to the second die using at least one through-silicon-via; providing a second device including a third die and fourth die, where the third die is diced from a third wafer, the fourth die is diced from a fourth wafer, the third die is connected to the fourth die using at least one through-silicon-via; where the first die includes a first functionality and the third die includes a second functionality, the first functionality is different than the second functionality, a majority of the masks used for processing the first wafer and the third wafer are the same; and the second die size is substantially different than the fourth die size.
1. A method of manufacturing semiconductor devices: providing a first device comprising a first die and a second die, wherein said first die is diced from a first wafer and said second die is diced from a second wafer and said first die is connected to said second die using at least one through-sili
1. A method of manufacturing semiconductor devices: providing a first device comprising a first die and a second die, wherein said first die is diced from a first wafer and said second die is diced from a second wafer and said first die is connected to said second die using at least one through-silicon-via (TSV);providing a second device comprising a third die and a fourth die, wherein said third die is diced from a third wafer and said fourth die is diced from a fourth wafer and said third die is connected to said fourth die using at least one through-silicon-via (TSV); wherein said first die comprises a first functionality and said third die comprises a second functionality,wherein said first functionality is different than said second functionality,wherein a majority of the masks used for processing said first wafer and said third wafer are the same;wherein said second die comprises a first amount of logic, or device input-output cells or memory, andwherein said fourth die comprises a second amount of logic, or device input-output cells or memory, said second amount is substantially different than said first amount. 2. The method to construct devices according to claim 1, wherein said first die is a field programmable gate array (FPGA) die. 3. The method to construct devices according to claim 1, wherein said second die comprises a configurable I/O die for the connection of said device to external devices. 4. The method to construct devices according to claim 1, wherein said second die comprises a memory die. 5. The method to construct devices according to claim 1, wherein said first die comprises a repeating array of functional units, wherein each of said functional units comprises a micro controller unit (MCU) and wherein at least one of said micro controller unit is used for the devices set up. 6. The method to construct devices according to claim 1, wherein dicing of said first die from said first wafer comprises an etch step to define dice lines. 7. The method to construct devices according to claim 1, wherein dicing of said first die from said first wafer comprises the use of a portion of the potential dice lines of said first wafer. 8. The method to construct devices according to claim 1, wherein said first die size is substantially different than said third die size. 9. A method of manufacturing semiconductor devices: providing a first device comprising a first die and a second die, wherein said first die is diced from a first wafer and said second die is diced from a second wafer and said first die is connected to said second die using at least one through-silicon-via (TSV);providing a second device comprising a third die and a fourth die, wherein said third die is diced from a third wafer and said fourth die is diced from a fourth wafer and said third die is connected to said fourth die using at least one through-silicon-via (TSV); wherein said first die comprises a first functionality and said third die comprises a second functionality,wherein said first functionality is different than said second functionality,wherein a majority of the masks used for processing said first wafer and said third wafer are the same; andwherein said second die size is substantially different than said fourth die size. 10. The method to construct devices according to claim 9, wherein said first die is a field programmable gate array (FPGA) die. 11. The method to construct devices according to claim 9, wherein said second die comprises an I/O die for the connection of said device to external devices. 12. The method to construct devices according to claim 9, wherein dicing of said second die from said second wafer comprises an etch step to define dice lines. 13. A method of manufacturing semiconductor devices: providing a first device comprising a first die and a second die, wherein said first die is diced from a first wafer and said second die is diced from a second wafer and said first die is connected to said second die using at least one through-silicon-via (TSV);providing a second device comprising a third die and a fourth die, wherein said third die is diced from a third wafer and said fourth die is diced from a fourth wafer and said third die is connected to said fourth die using at least one through-silicon-via (TSV); wherein said second die comprises an I/O die for the connection of said device to external devices,wherein said first die comprises a first functionality and said third die comprises a second functionality,wherein said first functionality is different than said second functionality,wherein a majority of the masks used for processing said first wafer and said third wafer are the same;wherein said second die comprises a first amount of logic, or device input-output cells or memory, andwherein said fourth die comprises a second amount of logic, or device input-output cells or memory, said second amount is substantially different than said first amount. 14. The method to construct devices according to claim 13, wherein said first die is a field programmable gate array (FPGA) die. 15. The method to construct devices according to claim 13, wherein said first die comprises a repeating array of functional units, wherein each of said functional units comprises a micro controller unit (MCU) and wherein at least one of said micro controller unit is used for the devices set up. 16. The method to construct devices according to claim 13, wherein dicing of said first die from said first wafer comprises an etch step to define dice lines. 17. The method to construct devices according to claim 13, wherein dicing of said first die from said first wafer comprises the use of a portion of the potential dice lines of said first wafer. 18. The method to construct devices according to claim 13, wherein said first die size is substantially different than said third die size. 19. A method of manufacturing semiconductor devices: providing a first device comprising a first die and a second die, wherein said first die is diced from a first wafer and said second die is diced from a second wafer and said first die is connected to said second die using at least one through-silicon-via (TSV);providing a second device comprising a third die and a fourth die, wherein said third die is diced from a third wafer and said fourth die is diced from a fourth wafer and said third die is connected to said fourth die using at least one through-silicon-via (TSV); wherein said second die comprises a memory die,wherein said first die comprises a first functionality and said third die comprises a second functionality,wherein said first functionality is different than said second functionality,wherein a majority of the masks used for processing said first wafer and said third wafer are the same; andwherein said second die size is substantially different than said fourth die size. 20. The method to construct devices according to claim 19, wherein said first die is a field programmable gate array (FPGA) die. 21. The method to construct devices according to claim 19, wherein dicing of said first die from said first wafer comprises the use of a portion of potential dice lines of said first wafer. 22. The method to construct devices according to claim 19, wherein dicing of said second die from said second wafer comprises an etch step to define dice lines. 23. The method to construct devices according to claim 19, wherein said first die comprises a repeating array of functional units, wherein each of said functional units comprises a micro controller unit (MCU) and wherein at least one of said micro-controller unit is used for the devices set up.
Copyright KISTI. All Rights Reserved.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.