Microchips with an internal hardware firewall that by its location leaves unprotected microprocessors or processing units which performs processing with a network
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-015/16
G06F-017/00
출원번호
US-0018089
(2011-01-31)
등록번호
US-8726303
(2014-05-13)
발명자
/ 주소
Ellis, III, Frampton E.
출원인 / 주소
Ellis, III, Frampton E.
대리인 / 주소
DLA Piper LLP US
인용정보
피인용 횟수 :
11인용 특허 :
178
초록▼
A microchip comprising an internal hardware firewall located between a protected portion of the microchip that is protected by the internal hardware firewall and a network portion that is configured to connect to a network of computers. The internal hardware firewall is configured to deny access to
A microchip comprising an internal hardware firewall located between a protected portion of the microchip that is protected by the internal hardware firewall and a network portion that is configured to connect to a network of computers. The internal hardware firewall is configured to deny access to the protected portion from the network. The microchip may also include one or more of a network communications, graphics, video, sound, hard drive, optical disk drive and flash memory component in the network portion and one or many microprocessors that are not network communications components and are in the network portion and are separate from the internal hardware firewall. The location of the internal hardware firewall permits unrestricted access by the network to the network portion so that processing operations other than network communications and firewall operations conducted by the microchip with the network are executed by the microprocessors in the network portion.
대표청구항▼
1. A microchip, comprising: a microprocessor configured to be a master controlling device of said computer;an internal hardware firewall located between a protected portion of said microchip that is protected by said internal hardware firewall and a network portion of said microchip, said network po
1. A microchip, comprising: a microprocessor configured to be a master controlling device of said computer;an internal hardware firewall located between a protected portion of said microchip that is protected by said internal hardware firewall and a network portion of said microchip, said network portion being configured to connect to a network of computers including the World Wide Web and/or the Internet; said internal hardware firewall is configured to deny access to at least said protected portion of said microchip from said network; andnetwork communications components located in said network portion of said microchip; andone or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors that are not network communications components, wherein said one or more microprocessors are located in said network portion of said microchip and are separate from said internal hardware firewall; andwherein the location of said internal hardware firewall permits unrestricted access by said network of computers to said network portion of said microchip so that processing operations other than network communications and firewall operations conducted by said microchip with the network of computers are executed by one or more of said microprocessors in said network portion of said microchip. 2. The microchip of claim 1, further comprising at least one microprocessor located in said protected portion of said microchip; and wherein said at least one microprocessor located in said protected portion of said microchip is separate from said internal hardware firewall and said internal hardware firewall is also configured to deny access to said at least at least one microprocessor located in said protected portion of said microchip by a network. 3. The microchip of claim 2, further comprising at least a non-volatile memory located in said protected portion of said microchip. 4. The microchip of claim 3, wherein one said microprocessor located in said protected portion of said microchip is configured to be a master controlling device of said microchip. 5. The microchip of claim 1, wherein said one or more microprocessors located in said network portion of said computer are not firewall components. 6. The microchip of claim 2, wherein the microchip is configured for a personal computer configured for control by an individual personal user. 7. A microchip, comprising: an internal hardware firewall located between a protected portion of said microchip that is protected by said internal hardware firewall and a network portion of said microchip, said network portion being configured to connect to a network of computers;at least one graphics component located in said network portion of the microchip;one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 processing units located in said network portion of said microchip, wherein said one or more processing units and said at least one graphics component are separate from each other and are each separate from said internal hardware firewall. 8. The microchip of claim 7, further comprising at least one processing unit located in said protected portion of said microchip; and wherein said at least one processing unit located in said protected portion of said microchip is separate from said internal hardware firewall and said internal hardware firewall is also configured to deny access to said at least one processing unit located in said protected portion of said microchip by a network. 9. The microchip of claim 8, wherein said at least one processing unit located in said protected portion of said microchip includes a master controlling device for the microchip. 10. The microchip of claim 7, wherein at least one network communications component is located in said network portion of the microchip and is separate from said internal hardware firewall and said at least one graphics component. 11. The microchip of claim 7, wherein at least one video component is located in said network portion of the microchip and is separate from said internal hardware firewall and said at least one graphics component. 12. The microchip of claim 7, wherein at least one sound component is located in said network portion of the microchip and is separate from said internal hardware firewall and said at least one graphics component. 13. The microchip of claim 7, wherein at least one flash memory component is located in said network portion of the microchip and is separate from said internal hardware firewall and said at least one graphics component. 14. The microchip of claim 7, wherein said internal hardware firewall is configured to deny access to at least said protected portion of said microchip from said network. 15. The microchip of claim 7, further comprising a microprocessor configured to be a master controlling device of said microchip. 16. The microchip of claim 15, wherein the microprocessor configured to be a master controlling device of said microchip is located in said protected portion of said microchip. 17. A microchip configured for a personal computer configured for control by an individual personal user to communicate with a network, said microchip comprising: an internal hardware firewall configured so that one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors of the microchip are not protected by said internal hardware firewall; and said one or more microprocessors that are not protected by said internal hardware firewall are separate from network communications components and said internal hardware firewall;said internal hardware firewall is configured to deny access to at least one protected portion of said microchip from said network; andsaid internal hardware firewall is configured by its location to permit unrestricted access by the network to said one or more microprocessors that are not protected by said internal hardware firewall, so that processing operations controlled by said personal user, other than network communication and firewall operations, that are conducted by said computer microchip with the network are executed by one or more said microprocessors that are not protected by said internal hardware firewall. 18. The microchip of claim 17, wherein said one or more microprocessors of the computer that are not protected by said internal hardware firewall are not firewall components. 19. The microchip of claim 17, wherein the microchip comprises a microprocessor configured to be a master controlling device of said microchip. 20. The microchip of claim 19, wherein the microprocessor configured to be a master controlling device of said microchip is located in said protected portion of said microchip. 21. The microchip of claim 17, further comprising a microprocessor located in the protected portion is configured to be a master controlling device of said microchip. 22. A microchip, comprising: an internal hardware firewall located between a protected portion of said microchip that is protected by said internal hardware firewall and a network portion of said microchip, said network portion being configured to connect to a network of computers;said internal hardware firewall is configured to deny access to at least said protected portion of said microchip from said network;one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors located in said network portion of said microchip, wherein said one or more microprocessors located in said network portion are separate from network communications components and said internal hardware firewall; andat least one graphics component is located in said network portion of the microchip and is separate from said internal hardware firewall; andwherein the location of said internal hardware firewall permits unrestricted access by said network of computers to said network portion of said microchip so that processing operations conducted by said microchip with the network of computers are executed by one or more said microprocessors in said network portion of said microchip and by said at least one graphics component in said network portion of said microchip. 23. The microchip of claim 22, further comprising a microprocessor configured to be a master controlling device of said microchip located in said protected portion of said microchip. 24. The microchip of claim 22, comprising a microprocessor configured to be a master controlling device of said microchip. 25. A microchip, comprising: an internal hardware firewall located between a protected portion of said microchip that is protected by said internal hardware firewall and a network portion of said microchip, said network portion being configured to connect to a network of computers;said internal hardware firewall is configured to deny access to at least said protected portion of said microchip from said network;one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors located in said network portion of said microchip, wherein said one or more microprocessors located in said network portion are separate from network communications components and said internal hardware firewall; andat least one video component is located in said network portion of the microchip and is separate from said internal hardware firewall; andwherein the location of said internal hardware firewall permits unrestricted access by said network of computers to said network portion of said microchip so that processing operations conducted by said microchip with the network of computers are executed by one or more said microprocessors in said network portion of said microchip and by said at least one video component in said network portion of said microchip. 26. The microchip of claim 25, further comprising a microprocessor configured to be a master controlling device of said microchip located in said protected portion of said microchip. 27. The microchip of claim 25, comprising a microprocessor configured to be a master controlling device of said microchip. 28. A microchip, comprising: an internal hardware firewall located between a protected portion of said microchip that is protected by said internal hardware firewall and a network portion of said microchip, said network portion being configured to connect to a network of computers;said internal hardware firewall is configured to deny access to at least said protected portion of said microchip from said network;one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors located in said network portion of said microchip, wherein said one or more microprocessors located in said network portion are separate from network communications components and said internal hardware firewall; andat least one sound component is located in said network portion of the microchip and is separate from said internal hardware firewall; andwherein the location of said internal hardware firewall permits unrestricted access by said network of computers to said network portion of said microchip so that processing operations conducted by said microchip with the network of computers are executed by one or more said microprocessors in said network portion of said microchip and by said at least one sound component in said network portion of said microchip. 29. The microchip of claim 28, further comprising a microprocessor configured to be a master controlling device of said microchip located in said protected portion of said microchip. 30. The microchip of claim 28, comprising a microprocessor configured to be a master controlling device of said microchip. 31. A microchip, comprising: an internal hardware firewall located between a protected portion of said microchip that is protected by said internal hardware firewall and a network portion of said microchip, said network portion being configured to connect to a network of computers;said internal hardware firewall is configured to deny access to at least said protected portion of said microchip from said network;one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors located in said network portion of said microchip, wherein said one or more microprocessors located in said network portion are separate from network communications components and said internal hardware firewall; andat least one hard drive component is located in said network portion of the microchip and is separate from said internal hardware firewall; andwherein the location of said internal hardware firewall permits unrestricted access by said network of computers to said network portion of said microchip so that processing operations conducted by said microchip with the network of computers are executed by one or more said microprocessors in said network portion of said microchip using said at least one hard drive component in said network portion of said microchip. 32. The microchip of claim 31, further comprising a microprocessor configured to be a master controlling device of said microchip located in said protected portion of said microchip. 33. The microchip of claim 31, comprising a microprocessor configured to be a master controlling device of said microchip. 34. A microchip, comprising: an internal hardware firewall located between a protected portion of said microchip that is protected by said internal hardware firewall and a network portion of said microchip, said network portion being configured to connect to a network of computers;said internal hardware firewall is configured to deny access to at least said protected portion of said microchip from said network;one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors located in said network portion of said microchip, wherein said one or more microprocessors located in said network portion are separate from network communications components and said internal hardware firewall; andat least one optical disk drive component is located in said network portion of the microchip and is separate from said internal hardware firewall; andwherein the location of said internal hardware firewall permits unrestricted access by said network of computers to said network portion of said microchip so that processing operations conducted by said microchip with the network of computers are executed by one or more said microprocessors in said network portion of said microchip using said at least one optical disk drive component in said network portion of said microchip. 35. The microchip of claim 34, further comprising a microprocessor configured to be a master controlling device of said microchip located in said protected portion of said microchip. 36. The microchip of claim 34, comprising a microprocessor configured to be a master controlling device of said microchip. 37. A microchip, comprising: an internal hardware firewall located between a protected portion of said microchip that is protected by said internal hardware firewall and a network portion of said microchip, said network portion being configured to connect to a network of computers;said internal hardware firewall is configured to deny access to at least said protected portion of said microchip from said network;one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors located in said network portion of said microchip, wherein said one or more microprocessors located in said network portion are separate from network communications components and said internal hardware firewall; andat least one flash memory component is located in said network portion of the microchip and is separate from said internal hardware firewall; andwherein the location of said internal hardware firewall permits unrestricted access by said network of computers to said network portion of said microchip so that processing operations conducted by said microchip with the network of computers are executed by one or more said microprocessors in said network portion of said microchip using said at least one flash memory component in said network portion of said microchip. 38. The microchip of claim 37, further comprising a microprocessor configured to be a master controlling device of said microchip is located in said protected portion of said microchip. 39. The microchip of claim 37, comprising a microprocessor configured to be a master controlling device of said microchip. 40. A microchip configured for a personal computer configured to communicate with a network, said microchip comprising: an internal hardware firewall configured so that one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors of the microchip are not protected by said internal hardware firewall; and said one or more microprocessors that are not protected by said internal hardware firewall are separate from network communications components and said internal hardware firewall;said internal hardware firewall is configured to deny access to at least one protected portion of said microchip from said network;said internal hardware firewall is configured by its location to permit unrestricted access by the network to said one or more microprocessors that are not protected by said internal hardware firewall, so that processing operations other than network communications and firewall operations conducted by said microchip with the network are executed by said one or more microprocessors that are not protected by said internal hardware firewall; andsaid operations include network browsing functions. 41. The microchip of claim 40, wherein said network browsing functions are selected from the group consisting of World Wide Web or Internet searching, email and conferencing. 42. The microchip of claim 40, comprising a microprocessor configured to be a master controlling device of said microchip. 43. A microchip configured for a personal computer configured to communicate with a network, said personal computer comprising: an internal hardware firewall configured so that one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 processing units of the microchip that are not network communications components are not protected by said internal hardware firewall; and said one or more processing units that are not protected by said internal hardware firewall are separate from network communications components and said internal hardware firewall; andsaid internal hardware firewall is configured by its location to permit unrestricted access by the network to said one or more processing units that are not protected by said internal hardware firewall, so that processing operations, other than network communications and firewall operations, that are conducted by said microchip with the network are executed by said one or more processing units that are not protected by said internal hardware firewall. 44. The microchip of claim 43, wherein said one or more processing units of the microchip that are not protected by said internal hardware firewall are not firewall components. 45. The microchip of claim 43, further comprising a microprocessor configured to be a master controlling device of said microchip. 46. The microchip of claim 14, wherein the microprocessor configured to be a master controlling device of said microchip is located in said protected portion of said microchip. 47. The microchip of claim 43, wherein the personal computer is also configured for control by an individual user and wherein processing operations controlled by said personal user, other than network communications and firewall operations, that are conducted by said microchip with the network are executed by said one or more processing units that are not protected by said internal hardware firewall. 48. A microchip configured for a personal computer configured to communicate with a network, said personal computer comprising: an internal hardware firewall configured so that one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 processing units of the microchip are not protected by said internal hardware firewall; and said one or more processing units that are not protected by said internal hardware firewall are separate from network communications components and said internal hardware firewall;said internal hardware firewall configured by its location to permit unrestricted access by the network to said one or more processing units, so that operations, other than network communications and firewall operations, conducted by said microchip with the network are executed by said one or more processing units that are not protected by said internal hardware firewall; andsaid operations other than network communications and firewall operations include network browsing functions. 49. The microchip of claim 48, wherein said network browsing functions are selected from the group consisting of World Wide Web or Internet searching, email and conferencing. 50. The microchip of claim 48, further comprising a microprocessor configured to be a master controlling device of said microchip. 51. The microchip of claim 50, wherein the microprocessor configured to be a master controlling device of said microchip is located in said protected portion of said microchip. 52. The microchip of claim 48, wherein the personal computer is also configured for control by an individual user and wherein operations controlled by said personal user, other than network communications and firewall operations, that are conducted by said microchip with the network are executed by said one or more processing units that are not protected by said internal hardware firewall.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (178)
Nielsen Keith E. (Redondo Beach CA), Active energy control for diode pumped laser systems using pulsewidth modulation.
Benkeser Donald E. (Naperville IL) Cyr Joseph B. (Aurora IL) Greenberg Albert G. (Millburn NJ) Wright Paul E. (Basking Ridge NJ), Adaptive job scheduling for multiprocessing systems with master and slave processors executing tasks with opposite antic.
Bonneau ; Jr. Walt C. (Missouri City TX) Guttag Karl (Missouri City TX) Gove Robert (Dallas TX), Architecture of a chip having multiple processors and multiple memories.
Russell David S. (Minneapolis MN) Fischer Larry G. (Waseca MN) Wala Philip M. (Waseca MN) Ratliff Charles R. (Crystal Lake IL) Brennan Jeffrey (Waseca MN), Cellular communications system with centralized base stations and distributed antenna units.
Naedel Richard G. (Rockville MD) Harris David B. (Columbia MD) Uehling Mark (Bowie MD), Chassis and personal computer for severe environment embedded applications.
Berkowitz David B. (Palo Alto CA) Hao Ming C. (Los Altos CA) Lieu Hung C. (Santa Clara CA) Snow Franklin D. (Saratoga CA), Collaborative computing system using pseudo server process to allow input from different server processes individually a.
Sumimoto Shinji (Kawasaki JPX), Computer resource distributing method and system for distributing a multiplicity of processes to a plurality of computer.
Passera Anthony ; Thorp John R. ; Beckerle Michael J. ; Zyszkowski Edward S. A., Computer system and computerized method for partitioning data for parallel processing.
Jones Oliver (Andover MA) Deshon Mary (Winthrop MA) Ericsson Staffan (Brookline MA) Flach James (Cave Creek AZ), Computer teleconferencing method and apparatus.
Ellis, III, Frampton E., Computers and microchips with a faraday cage, a side protected by an internal hardware firewall and an unprotected side connected to the internet for network operations, and with internal hardware compartments.
Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall and an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary inner hardware firewalls.
Glick James A. (Granite Shoals TX) Graczyk Ronald B. (Round Rock TX) Nurick Albert F. (Austin TX) Fraley Brittain D. (Austin TX), Computing and multimedia entertainment system.
Leung Wing Y. (Cupertino CA) Hsu Fu-Chieh (Saratoga CA), Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale in.
Morley Richard E. (Greenville NH), Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and met.
Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Riegelhaupt Norbert H. (Framingham MA), Dual-rail processor with error checking at single rail interfaces.
Rosenberry Steven (Reading PA), Dynamic fault-tolerant parallel processing system for performing an application function with increased efficiency using.
Pian Chao-Kuang (Anaheim CA) Habereder Hans L. (Orange CA), Dynamic task allocation in a multi-processor system employing distributed control processors and distributed arithmetic.
Pezeshki Bardia (Huntington Beach CA) Harris ; Jr. James S. (Stanford CA), Electrostatically tunable optical device and optical interconnect for processors.
Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Fully scalable parallel processing system having asynchronous SIMD processing.
Nguyen Tam M. (Valhalla NY) Rana Deepak (Yorktown Heights NY) Ruiz Antonio (Yorktown Heights NY) Willner Barry E. (Briarcliff Manor NY), Hybrid digital/analog multimedia hub with dynamically allocated/released channels for video processing and distribution.
Fucito Michele (Meta ITX) Recchia Maruo (Rome ITX) Puglia Silvestro (Pomezia ITX) Mariani Claudio (Rome ITX) Colangeli Giulio (Gerenzano di Roma ITX) Rotunno Antonio (Salerno ITX), Interface unit for dynamically configuring a buffer in different modes to store data transfers based upon different conn.
Guy Charles B. (Hillsboro OR) Cadambi Sudarshan B. (Beaverton OR) Gutmann Michael J. (Portland OR) Bhasker Narjala (Portland OR) Trethewey Jim R. (Beaverton OR) McArdle Brian J. (Beaverton OR), Interrupt distribution scheme for a computer bus.
Wade Jon P. ; Cassiday Daniel R. ; Lordi Robert D. ; Steele ; Jr. Guy Lewis ; St. Pierre Margaret A. ; Wong-Chan Monica C. ; Abuhamdeh Zahi S. ; Douglas David C. ; Ganmukhi Mahesh N. ; Hill Jeffrey V, Massively parallel computer including auxiliary vector processor.
Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L., Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network an.
Bruckert William (Northboro MA) Kovalcin David (Grafton MA) Bissett Thomas D. (Derry NH) Munzer John (Brookline MA) Mazur Dennis (Worcester MA) Mott ; Jr. Peter R. (Worcester MA) Dearth Glenn A. (Hud, Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having.
Ault Donald Fred ; Bender Ernest Scott ; Spiegel Michael Gary, Method and apparatus for creating a security environment for a user task in a client/server system.
Kisor Greg, Method and system including a central computer that assigns tasks to idle workstations using availability schedules and computational capabilities.
Farnworth Warren M. (Boise ID) Duesman Kevin (Boise ID) Heitzeberg Ed (Boise ID), Method for fabricating wafer-scale integration wafers and method for utilizing defective wafer-scale integration wafers.
Rausch Dieter (Karlsruhe DEX), Method for preventing an overload when starting a multicomputer system and multicomputer system for carrying out said me.
Shorter David U. (Lewisville TX), Method for scheduling execution of distributed application programs at preset times in an SNA LU 6.2 network environment.
Harris Jonathan P. (Littleton MA) Leibholz Daniel (Watertown MA) Miller Brad (Westborough MA), Method of dynamically allocating processors in a massively parallel processing system.
Ellis, Frampton E., Method of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
Ellis, Frampton E., Methods of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
Hu Ming K. (Syracuse NY) Jia Yau G. (Nanjing ; Jiangsu CNX), Microprogram-coupled multiple-microprocessor module with 32-bit byte width formed of 8-bit byte width microprocessors.
Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Rolfe David Bruce, N-dimensional modified hypercube.
Hodge Winston W. (Yorba Linda CA) Taylor Lawrence E. (Anaheim CA), Near-video-on-demand digital video distribution system utilizing asymmetric digital subscriber lines.
Georgiou,Christos J.; Gregurick,Victor L.; Nair,Indira; Salapura,Valentina, Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus.
Hinsley Christopher Andrew,GBX, Operating system for use with computer networks incorporating one or more data processors linked together for parallel p.
Chin Danny (Robbinsville NJ) Sauer Donald J. (Allentown NJ) Meyerhofer Dietrich (Princeton NJ) Katsuki Kazuo (Hyogo JPX), Parallel digital processing system using optical interconnection between control sections and data processing sections.
Beatty Harry J. (Clinton Corners NY) Elmendorf Peter C. (Kingston NY) Gillis Roland R. (Ulster Park NY) Pramanick Ira (Wappingers Falls NY), Parallel execution of a complex task partitioned into a plurality of entities.
Beatty Harry John ; Elmendorf Peter Claude ; Gillis Roland Roberto ; Pramanick Ira, Parallel execution of a complex task partitioned into a plurality of entities.
Bahr James E. (Rochester MN) Corrigan Michael J. (Rochester MN) Knipfer Diane L. (Rochester MN) McMahon Lynn A. (Rochester MN) Metzger Charlotte B. (Elgin MN), Process for dispatching tasks among multiple information processors.
Nelson Darul J. ; Noval James V. ; Suarez Ricardo E. ; Aghazadeh Mostafa A., Processor card assembly including a heat sink attachment plate and an EMI/ESD shielding cage.
Gregerson Daniel P. ; Farrell David R. ; Gaitonde Sunil S. ; Ahuja Ratinder P. ; Ramakrishnan Krish ; Shafiq Muhammad ; Wallis Ian F., Scalable distributed computing environment.
Ohta Hiroyuki,JPX ; Miura Hideo,JPX ; Usami Mitsuo,JPX ; Kametani Masatsugu,JPX ; Zen Munetoshi,JPX ; Okamoto Noriaki,JPX, Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same.
Danahy John J. ; Kinney Daryl F. ; Pulsinelli Gary S. ; Rose Lawrence J. ; Kumar Navaneet, Service-centric monitoring system and method for monitoring of distributed services in a computing network.
Hoover Russell D. (Rochester MN) Willis John C. (Rochester MN) Baldus Donald F. (Mazeppa MN) Ziegler Frederick J. (Rochester MN) Liu Lishing (Pleasantville NY), System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data p.
Teper Jeffrey A. ; Koneru Sudheer ; Mangione Gordon ; Balaz Rudolph ; Contorer Aaron M. ; Chao Lucy, System and method for providing trusted brokering services over a distributed network.
Chasek Norman E. (24 Briar Brae Rd. Stamford CT 06903), System for developing real time economic incentives to encourage efficient use of the resources of a regulated electric.
Leclercq Thierry (Paris FRX) Sallio Patrick (Thorigne-Fouillard FRX), System for management of the usage of data consultations in a telecommunication network.
Choquier Philippe,FRX ; Peyroux Jean-Francios ; Griffin William J., System for on-line service in which gateway computer uses service map which includes loading condition of servers broad.
Baehr Geoffrey G. ; Danielson William ; Lyon Thomas L. ; Mulligan Geoffrey ; Patterson Martin,FRX ; Scott Glenn C. ; Turbyfill Carolyn, System for packet filtering of data packets at a computer network interface.
Shwed Gil,ILX ; Kramer Shlomo,ILX ; Zuk Nir,ILX ; Dogon Gil,ILX ; Ben-Reuven Ehud,ILX, System for securing the flow of and selectively modifying packets in a computer network.
Padgaonkar Ajay J. (Phoenix AZ) Mitra Sumit K. (Tempe AZ), System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory.
Kraft Reiner ; Lu Qi ; Wisebond Marat, Task distribution processing system and the method for subscribing computers to perform computing tasks during idle time.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.