초록

An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.

대표청구항 ▼

1. An integrated circuit structure comprising: a semiconductor substrate;a conductive via (TSV) passing through the semiconductor substrate;an interconnect structure overlying the semiconductor substrate;a metal pad directly overlying the interconnect structure;a first polyimide layer overlying the

1. An integrated circuit structure comprising: a semiconductor substrate;a conductive via (TSV) passing through the semiconductor substrate;an interconnect structure overlying the semiconductor substrate;a metal pad directly overlying the interconnect structure;a first polyimide layer overlying the metal pad;a second polyimide layer comprising a portion level with the interconnect structure, wherein the metal pad extends into the second polyimide layer and contacts the interconnect structure;an under-bump-metallurgy (UBM) directly coupled to the metal pad;a dielectric buffer layer between the first polyimide layer and the UBM, wherein the dielectric buffer layer comprises a first portion contacting the metal pad and a second portion over and separated from the metal pad; anda copper-containing post overlying the UBM layer, wherein the copper post is electrically connected to the conductive via. 2. The integrated circuit structure of claim 1 further comprising: a conductive barrier over the copper-containing post; anda solder over the conductive barrier. 3. The integrated circuit structure of claim 1 further comprising a metallic layer on the copper-containing post, wherein the metallic layer comprises a first portion directly over the copper-containing post, and a second portion on a sidewall of the copper-containing post. 4. The integrated circuit structure of claim 1, wherein the metal pad is connected to the UBM through a conductive feature in the dielectric buffer layer. 5. The integrated circuit structure of claim 1, wherein the copper-containing post has a thickness less than about 60 μm. 6. An integrated circuit structure comprising: a semiconductor substrate;a conductive via extending from a front surface to a back surface of the semiconductor substrate;an interconnect structure overlying the front surface of the semiconductor substrate, wherein the interconnect structure comprises copper;an aluminum-containing pad overlying the semiconductor substrate;a first polyimide layer over the aluminum-containing pad;a second polyimide layer overlying the interconnect structure, the second polyimide layer having an upper surface coplanar with an upper surface of the aluminum-containing pad;an under-bump-metallurgy (UBM) over and connected to the aluminum-containing pad;a dielectric buffer layer between the first polyimide layer and the UBM, wherein the dielectric buffer layer comprises a first portion contacting the aluminum-containing pad and a second portion over and separated from the aluminum-containing pad; anda copper-containing post overlying the front surface of the semiconductor substrate and electrically connected to the conductive via and the interconnect structure. 7. The integrated circuit structure of claim 6, wherein a thickness of the copper-containing post is between about 55 μm and about 30 μm. 8. The integrated circuit structure of claim 6, wherein the UBM comprises an extension extending into the first polyimide layer and electrically connected to the aluminum-containing pad. 9. The integrated circuit structure of claim 6 further comprising: a conductive barrier over the copper-containing post; anda solder over the conductive barrier. 10. The integrated circuit structure of claim 6 further comprising a metal finish on the copper-containing post, wherein the metal finish comprises a first portion directly over the copper-containing post, and a second portion on a sidewall of the copper-containing post. 11. The integrated circuit structure of claim 10, wherein the metal finish comprises a metal selected from the group consisting essentially of tin, nickel, palladium, gold, and combinations thereof. 12. An integrated circuit structure comprising: a semiconductor substrate;a conductive via extending from a front surface to a back surface of the semiconductor substrate;an interconnect structure overlying the semiconductor substrate;a metal pad directly overlying the interconnect structure;an under-bump-metallurgy (UBM) directly coupled to the metal pad;a pair of polyimide layers overlying the interconnect structure;a dielectric buffer layer between the UBM and an uppermost layer of the pair of polyimide layers, wherein the dielectric buffer layer comprises a first portion contacting the metal pad and a second portion over the metal pad;a copper-containing post over the UBM layer, wherein the copper post is electrically connected to the conductive via; anda conductive barrier over the copper-containing post, wherein the conductive barrier, the copper-containing post, and the conductive via are electrically connected. 13. The integrated circuit structure of claim 12, wherein the UBM comprising a first portion coupled to the metal pad, and a second portion over the second portion of the dielectric buffer layer. 14. The integrated circuit structure of claim 12 further comprising a solder over the conductive barrier.