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ESD protection device with charge collections regions 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H02H-009/00
출원번호 US-0135335 (2008-06-09)
등록번호 US-8737027 (2014-05-27)
발명자 / 주소
  • Walker, Andrew J.
출원인 / 주소
  • Cypress Semiconductor Corporation
인용정보 피인용 횟수 : 0  인용 특허 : 56

초록

A device for providing electrostatic discharge (ESD) protection is described which includes a silicon controlled rectifier (SCR), a mechanism for triggering the SCR, and a pair of contact regions of opposing conductivity type distinct from regions of the SCR that are interposed between the cathodic

대표청구항

1. A device for providing electrostatic discharge (ESD) protection, comprising: a silicon controlled rectifier (SCR);a transistor implementing a mechanism for triggering the SCR;a pair of contact regions of opposing conductivity type distinct from the SCR and interposed between a cathodic region and

이 특허에 인용된 특허 (56)

  1. Chen Jerry (Taipei TWX), Apparatus for electro-static discharge protection in a semiconductor device.
  2. Watt Jeffrey T., Apparatus for smart power supply ESD protection structure.
  3. Watt Jeffrey T. (Mountain View CA), Apparatus for smart power supply ESD protection structure.
  4. Jeon,Chanhee; Kwon,Bongjae; Kwon,Eunkyoung, Buffer circuit having electrostatic discharge protection.
  5. Ker Ming D. (Hsinchu TWX) Lee Chung Y. (Chung-Li TWX) Wu Chung Y. (Hsinchu TWX) Ko Joe (Hsin-chu TWX), CMOS ESD protection circuit with parasitic SCR structures.
  6. Ker Ming-Dou (Hsinchu TWX) Lee Chung-Yuan (Hsinchu TWX) Wu Chung-Yu (Hsinchu TWX), CMOS on-chip ESD protection circuit and semiconductor structure.
  7. Ker Ming-Dou (Hsinchu TWX) Lee Chung-Yuan (Hsinchu TWX) Wu Chung-Yu (Hsinchu TWX), CMOS on-chip ESD protection circuit and semiconductor structure.
  8. Ker Ming-Dou,TWX ; Wu Tain-Shun,TWX, CMOS output buffer with enhanced high ESD protection capability.
  9. Co Ramon (Trabuco Canyon CA) Lee Kwok Fai V. (Irvine CA) Ouyang Kenneth W. (Huntington Beach CA), Capacitively induced electrostatic discharge protection circuit.
  10. Spenea, Marian Udrea; Bucur, Constantin; Niculae, Marian; Simion, George; Marinescu, Viorel, Circuit and method for trimming locking of integrated circuits.
  11. Scott David B. (Plano TX) Bosshart Patrick W. (Dallas TX) Gallia James D. (Dallas TX), Circuit to improve electrostatic discharge protection.
  12. Lee Jian-Hsing,TWX ; Liu Kuo-Chio,TWX, Combined NMOS and SCR ESD protection device.
  13. Ker Ming-Dou (Tainan Hsien TWX) Wu Chung-Yu (Hsinchu TWX) Chang Hun-Hsien (Taipei Hsien TWX) Lee Chung-Yuan (Chungli TWX) Ko Joe (Hsinchu TWX), Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits.
  14. Kim,Kil Ho, Device for electrostatic discharge protection and circuit thereof.
  15. Chan Tsiu C. (Carrollton TX) Culver David S. (The Colony TX), ESD protection circuit.
  16. Lee Kowk Fai V. (Irvine CA) Lee Alan (Irvine CA), ESD protection circuit with segmented buffer transistor.
  17. Wei Hua-Fang ; Kapoor Ashok, ESD protection for deep submicron CMOS devices with minimum tradeoff for latchup behavior.
  18. Smooha Yehuda (South Whitehall Twp. ; Lehigh County PA), ESD protection for output buffers.
  19. Brodsky, Jonathan; Steinhoff, Robert; Pendharkar, Sameer P., Efficient protection structure for reverse pin-to-pin electrostatic discharge.
  20. Song, Ki-Whan, Electrostatic discharge (ESD) protection circuit of silicon-controlled rectifier (SCR) structure operable at a low trigger voltage.
  21. Hou, Chien-Ti; Chiu, Fu-Chien; Chen, Wei-Fan, Electrostatic discharge protection apparatus.
  22. Chen Wei-Fan,TWX, Electrostatic discharge protection circuit with high trigger current.
  23. Leach Jerald G. (Houston TX), Electrostatic discharge protection in integrated circuits, systems and methods.
  24. Leach Jerald G. (Houston TX), Electrostatic discharge protection in integrated circuits, systems and methods.
  25. Cheng, Tao; Lee, Jian-Hsing, Embedded SCR protection device for output and input pad.
  26. Watt Jeffrey, Fast turn-on silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection.
  27. Teggatz Ross E. ; Devore Joseph A. ; Baldwin David J., High breakdown-voltage transistor with transient protection.
  28. Wang,Bin; Wang,Chih Hsin, High voltage FET gate structure.
  29. Croft Gregg D. (Palm Bay FL), High voltage protection using SCRs.
  30. Charvaka Duvvury ; Roy Clifton Jones, III, High voltage trigger remote-cathode SCR.
  31. Morton, Alec; Efland, Taylor; Tsai, Chin-yu; Mitros, Jozef C.; Mosher, Dan M.; Shichijo, Sam; Kunz, Keith, Higher voltage transistors for sub micron CMOS processes.
  32. Consiglio Rosario (San Jose CA) Ku Yen-Hui (Cupertino CA), Input-output (I/O) structure with capacitively triggered thyristor for electrostatic discharge (ESD) protection.
  33. Strauss Mark S. (Allentown PA), Integrated circuit with MOS capacitor for improved ESD protection.
  34. Racino Gregory A. (Austin TX) Obuszewski Kenneth (Austin TX), Integrated circuit with electrostatic discharge (ESD) protection and ESD protection circuit.
  35. Williams, Richard K.; Cornell, Michael E.; Chan, Wai Tien, Isolated complementary MOS devices in epi-less substrate.
  36. Chen, Fu-Hsin; Liu, Ruey-Hsin, LDMOS device with isolation guard rings.
  37. Vladislav Vashchenko ; Peter J. Hopper, LVTSCR with a holding voltage that is greater than a DC bias voltage on a to-be-protected node.
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  39. Avery Leslie R. (Flemington NJ), Low voltage triggered snap-back device.
  40. Chen Hung-Sheng (San Jose CA) Shyu Chin-Miin (San Jose CA) Teng C. S. (San Jose CA), Low voltage triggering silicon controlled rectifier structures for ESD protection.
  41. Ker, Ming-Dou; Lo, Wen-Yu; Chang, Hun-Hsien, Low-leakage diode string for use in the power-rail ESD clamp circuits.
  42. Chang,Chi Hsuen; Liu,Jun Xiu; Huang,Tsung Yi; Chen,Chung I; Sung,Tzu Chiang; Huang,Chih Po; Yeh,Rann Shyan, Method and apparatus for a semiconductor device having low and high voltage transistors.
  43. Li, Sheau-Suey; Toutounchi, Shahin; Hart, Michael J.; Wu, Xin X.; Gitlin, Daniel, Method of forming a zener diode.
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  45. Lee Jian-Hsing,TWX ; Wu Yi-Hsun,TWX ; Chen Shui-Hung,TWX ; Shih Jiaw-Ren,TWX, N-type structure for n-type pull-up and down I/O protection circuit.
  46. Salcedo,Javier A.; Liou,Juin J.; Bernier,Joseph C.; Whitney, Jr.,Donald K., On-chip structure for electrostatic discharge (ESD) protection.
  47. Roberts Gregory N. (Boise ID), Output ESD protection circuit.
  48. Lee Kwok Fai V. (Irvine CA), Power rail ESD protection circuit.
  49. Cheng Wen-Bor (Tainan TWX), Protection circuit against electrostatic discharge using SCR structure.
  50. Yu,Ta Lee, SCR-ESD structures with shallow trench isolation.
  51. Okawa, Kazuhiko; Saiki, Takayuki, Semiconductor device for electrostatic protection.
  52. Yang, Chung-Cheng, Shears.
  53. Walker, Andrew J.; Puchner, Helmut, Silicon controlled rectifier electrostatic discharge clamp for a high voltage laterally diffused MOS transistor.
  54. Yu, Ta Lee, Silicon-controlled rectifier structures on silicon-on insulator with shallow trench isolation.
  55. Chen Julian Zhiliang ; Vrotsos Thomas A. ; Chen Wayne T., Stacked silicon-controlled rectifier having a low voltage trigger and adjustable holding voltage for ESD protection.
  56. Jian-Hsing Lee TW; Kuo-Chio Liu TW; Bing-Lung Liao TW; Jiaw-Ren Shih TW, Uniform current distribution SCR device for high voltage ESD protection.
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