최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0007582 (2011-01-14) |
등록번호 | US-8759882 (2014-06-24) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 1 인용 특허 : 507 |
An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are position
An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending perpendicular to the first direction. Some of the three or more linear conductive segments within the gate electrode levels of the adjoining pair of dynamic array sections are co-aligned in the first direction and separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the adjoining pair of dynamic array sections. Each of these end-to-end spacings is sized to ensure that each gate electrode level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of the co-aligned linear conductive segments.
1. An integrated circuit device, comprising: a plurality of dynamic array sections each formed within a respective outer peripheral boundary defined by four or more outer peripheral boundary segments, wherein each of the plurality of dynamic array sections includes a respective gate electrode level
1. An integrated circuit device, comprising: a plurality of dynamic array sections each formed within a respective outer peripheral boundary defined by four or more outer peripheral boundary segments, wherein each of the plurality of dynamic array sections includes a respective gate electrode level that forms a portion of an overall gate electrode level of the integrated circuit device, wherein each of the plurality of dynamic array sections includes three or more linear conductive segments formed within its gate electrode level, wherein the three or more linear conductive segments are formed in a parallel manner to extend lengthwise in a first direction,wherein the plurality of dynamic array sections includes a first adjoining pair of dynamic array sections positioned to have co-located portions of outer peripheral boundary segments extending perpendicular to the first direction,wherein some of the three or more linear conductive segments within the gate electrode levels of the first adjoining pair of dynamic array sections are co-aligned in the first direction and separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections, andwherein each of the first adjoining pair of dynamic array sections is defined such that a respective gate electrode level manufacturing assurance halo portion extends in the first direction away from its co-located portion of outer peripheral boundary segment toward the other of the first adjoining pair of dynamic array sections, wherein each end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections is sized to ensure that each gate electrode level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of any portion of the co-aligned linear conductive segments. 2. An integrated circuit device as recited in claim 1, wherein each of the plurality of dynamic array sections is a separate integrated circuit cell. 3. An integrated circuit device as recited in claim 1, wherein the three or more linear conductive segments within the gate electrode levels of the first adjoining pair of dynamic array sections are formed according to a segment pitch that is substantially equal across the gate electrode levels of the first adjoining pair of dynamic array sections, wherein the segment pitch is defined as a centerline-to-centerline spacing as measured in a second direction perpendicular to the first direction between each pair of adjacently positioned linear conductive segments. 4. An integrated circuit device as recited in claim 3, wherein the outer peripheral boundary of each of the first adjoining pair of dynamic array sections includes two outer peripheral boundary segments that extend in the first direction, and wherein each of the first adjoining pair of dynamic array sections is defined to have a respective width as measured in the second direction between the two outer peripheral boundary segments that extend in the first direction, wherein the width is an integer multiple of the segment pitch. 5. An integrated circuit device as recited in claim 4, wherein at least one of the three or more linear conductive segments formed within the gate electrode level of a first dynamic array section of the first adjoining pair of dynamic array sections is positioned at each integer multiple of the segment pitch as measured in the second direction from either of the two outer peripheral boundary segments of the first dynamic array section that extend in the first direction, so as to be separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections from a co-aligned linear conductive segment in a second dynamic array section of the first adjoining pair of dynamic array sections. 6. An integrated circuit device as recited in claim 5, wherein at least one of the three or more linear conductive segments within the gate electrode level of the first dynamic array section does not form a gate electrode of a transistor. 7. An integrated circuit device as recited in claim 4, wherein at least one of the three or more linear conductive segments formed within the gate electrode level of a first dynamic array section of the first adjoining pair of dynamic array sections is positioned at each integer multiple of the segment pitch as measured in the second direction from a location that is one-half of the segment pitch outside of either of the two outer peripheral boundary segments of the first dynamic array section that extend in the first direction, so as to be separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections from a co-aligned linear conductive segment in a second dynamic array section of the first adjoining pair of dynamic array sections. 8. An integrated circuit device as recited in claim 7, wherein at least one of the three or more linear conductive segments within the gate electrode level of the first dynamic array section does not form a gate electrode of a transistor. 9. An integrated circuit device as recited in claim 1, wherein at least one of the three or more linear conductive segments within the gate electrode level of at least one of the plurality of dynamic array sections does not form a gate electrode of a transistor. 10. An integrated circuit device as recited in claim 1, wherein each end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections is of substantially equal size as measured in first direction. 11. An integrated circuit device as recited in claim 10, wherein a size of each gate electrode level manufacturing assurance halo portion as measured in the first direction is substantially equal to one-half of the end-to-end spacing size as measured in the first direction. 12. An integrated circuit device as recited in claim 1, wherein each gate electrode level manufacturing assurance halo portion is devoid of any portion of any linear conductive segment formed within the gate electrode level of either of the first adjoining pair of dynamic array sections. 13. An integrated circuit device as recited in claim 1, wherein each end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections is split in a substantially equal manner between the first adjoining pair of dynamic array sections. 14. An integrated circuit device as recited in claim 1, wherein some of the end-to-end spacings that span the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections are unequally split between the first adjoining pair of dynamic array sections. 15. An integrated circuit device as recited in claim 14, wherein each portion of each of the end-to-end spacings within a given one of the first adjoining pair of dynamic array sections is of substantially equal size as measured in the first direction. 16. An integrated circuit device as recited in claim 1, wherein the co-located portions of outer peripheral boundary segments extending perpendicular to the first direction includes a portion of a first boundary segment of a first dynamic array section of the first adjoining pair of dynamic array sections and a portion of a second boundary segment of a second dynamic array section of the first adjoining pair of dynamic array sections. 17. An integrated circuit device as recited in claim 1, wherein the co-located portions of outer peripheral boundary segments extending perpendicular to the first direction includes a portion of a first boundary segment of a first dynamic array section of the first adjoining pair of dynamic array sections and an entirety of a second boundary segment of a second dynamic array section of the first adjoining pair of dynamic array sections. 18. An integrated circuit device as recited in claim 1, wherein the co-located portions of outer peripheral boundary segments extending perpendicular to the first direction includes an entirety of a first boundary segment of a first dynamic array section of the first adjoining pair of dynamic array sections and an entirety of a second boundary segment of a second dynamic array section of the first adjoining pair of dynamic array sections. 19. An integrated circuit device as recited in claim 1, wherein the gate electrode levels of the first adjoining pair of dynamic array sections further include one or more continuous linear conductive segments that extend lengthwise in the first direction through the gate electrode level manufacturing assurance halo portions so as to extend continuously between the first adjoining pair of dynamic array sections. 20. An integrated circuit device as recited in claim 1, wherein each of the plurality of dynamic array sections includes a respective first interconnect level that forms a portion of an overall first interconnect level of the integrated circuit device, wherein each of the plurality of dynamic array sections includes a number of first interconnect linear conductive segments formed within its first interconnect level, wherein the number of first interconnect linear conductive segments are formed in a parallel manner to extend lengthwise in the first direction, and wherein some of the number of first interconnect linear conductive segments within the first interconnect levels of the first adjoining pair of dynamic array sections are co-aligned in the first direction and separated by a first interconnect end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections. 21. An integrated circuit device as recited in claim 20, wherein each of the first adjoining pair of dynamic array sections is defined such that a respective first interconnect level manufacturing assurance halo portion extends in the first direction away from its co-located portion of outer peripheral boundary segment toward the other of the first adjoining pair of dynamic array sections, wherein each first interconnect end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections is sized to ensure that each first interconnect level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of any portion of the co-aligned first interconnect linear conductive segments. 22. An integrated circuit device as recited in claim 20, wherein the first interconnect levels of the first adjoining pair of dynamic array sections further include one or more continuous first interconnect linear conductive segments that extend lengthwise in the first direction through the first interconnect level manufacturing assurance halo portions so as to extend continuously between the first adjoining pair of dynamic array sections. 23. An integrated circuit device as recited in claim 20, wherein each of the first adjoining pair of dynamic array sections is defined by a plurality of outer peripheral boundary segments extending in the first direction, and wherein the first interconnect level of at least one of the first adjoining pair of dynamic array sections includes an outermost first interconnect linear conductive segment foamed to overlap one of the plurality of outer peripheral boundary segments extending in the first direction. 24. An integrated circuit device as recited in claim 20, wherein each of the plurality of dynamic array sections includes a respective second interconnect level that forms a portion of an overall second interconnect level of the integrated circuit device, wherein each of the plurality of dynamic array sections includes a number of second interconnect linear conductive segments formed within its second interconnect level, wherein the number of second interconnect linear conductive segments are foamed in a parallel manner to extend lengthwise in a second direction perpendicular to the first direction, wherein the plurality of dynamic array sections includes a second adjoining pair of dynamic array sections positioned to have co-located portions of outer peripheral boundary segments extending in the first direction, andwherein some of the number of second interconnect linear conductive segments within the second interconnect levels of the second adjoining pair of dynamic array sections are co-aligned in the second direction and separated by a second interconnect end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the second adjoining pair of dynamic array sections. 25. An integrated circuit device as recited in claim 24, wherein each of the second adjoining pair of dynamic array sections is defined such that a respective second interconnect level manufacturing assurance halo portion extends in the second direction away from its co-located portion of outer peripheral boundary segment toward the other of the second adjoining pair of dynamic array sections, wherein each second interconnect end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the second adjoining pair of dynamic array sections is sized to ensure that each second interconnect level manufacturing assurance halo portion of the second adjoining pair of dynamic array sections is devoid of any portion of the co-aligned second interconnect linear conductive segments. 26. An integrated circuit device as recited in claim 25, wherein the second adjoining pair of dynamic array sections includes one of the first adjoining pair of dynamic array sections. 27. An integrated circuit device as recited in claim 24, wherein the co-located portions of outer peripheral boundary segments extending in the first direction includes a portion of a first boundary segment of a first dynamic array section of the second adjoining pair of dynamic array sections and a portion of a second boundary segment of a second dynamic array section of the second adjoining pair of dynamic array sections. 28. An integrated circuit device as recited in claim 24, wherein the co-located portions of outer peripheral boundary segments extending in the first direction includes a portion of a first boundary segment of a first dynamic array section of the second adjoining pair of dynamic array sections and an entirety of a second boundary segment of a second dynamic array section of the second adjoining pair of dynamic array sections. 29. An integrated circuit device as recited in claim 24, wherein the co-located portions of outer peripheral boundary segments extending in the first direction includes an entirety of a first boundary segment of a first dynamic array section of the second adjoining pair of dynamic array sections and an entirety of a second boundary segment of a second dynamic array section of the second adjoining pair of dynamic array sections. 30. An integrated circuit device as recited in claim 24, wherein the second interconnect levels of the second adjoining pair of dynamic array sections further include one or more continuous second interconnect linear conductive segments that extend lengthwise in the second direction through the second interconnect level manufacturing assurance halo portions so as to extend continuously between the second adjoining pair of dynamic array sections. 31. An integrated circuit device as recited in claim 24, wherein each of the second adjoining pair of dynamic array sections is defined by a plurality of outer peripheral boundary segments extending in the second direction, and wherein the second interconnect level of at least one of the second adjoining pair of dynamic array sections includes an outermost second interconnect linear conductive segment formed to overlap one of the plurality of outer peripheral boundary segments extending in the second direction. 32. An integrated circuit device as recited in claim 1, wherein each of the plurality of dynamic array sections includes a respective first interconnect level that forms a portion of an overall first interconnect level of the integrated circuit device, wherein each of the plurality of dynamic array sections includes a number of first interconnect linear conductive segments formed within its first interconnect level, wherein the number of first interconnect linear conductive segments are formed in a parallel manner to extend lengthwise in a second direction perpendicular to the first direction, wherein the plurality of dynamic array sections includes a second adjoining pair of dynamic array sections positioned to have co-located portions of outer peripheral boundary segments extending in the first direction, andwherein some of the number of first interconnect linear conductive segments within the first interconnect levels of the second adjoining pair of dynamic array sections are co-aligned in the second direction and separated by a first interconnect end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the second adjoining pair of dynamic array sections. 33. An integrated circuit device as recited in claim 32, wherein each of the second adjoining pair of dynamic array sections is defined such that a respective first interconnect level manufacturing assurance halo portion extends in the second direction away from its co-located portion of outer peripheral boundary segment toward the other of the second adjoining pair of dynamic array sections, wherein each first interconnect end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the second adjoining pair of dynamic array sections is sized to ensure that each first interconnect level manufacturing assurance halo portion of the second adjoining pair of dynamic array sections is devoid of any portion of the co-aligned first interconnect linear conductive segments. 34. An integrated circuit device as recited in claim 33, wherein the second adjoining pair of dynamic array sections includes one of the first adjoining pair of dynamic array sections. 35. An integrated circuit device as recited in claim 32, wherein the co-located portions of outer peripheral boundary segments extending in the first direction includes a portion of a first boundary segment of a first dynamic array section of the second adjoining pair of dynamic array sections and a portion of a second boundary segment of a second dynamic array section of the second adjoining pair of dynamic array sections. 36. An integrated circuit device as recited in claim 32, wherein the co-located portions of outer peripheral boundary segments extending in the first direction includes a portion of a first boundary segment of a first dynamic array section of the second adjoining pair of dynamic array sections and an entirety of a second boundary segment of a second dynamic array section of the second adjoining pair of dynamic array sections. 37. An integrated circuit device as recited in claim 32, wherein the co-located portions of outer peripheral boundary segments extending in the first direction includes an entirety of a first boundary segment of a first dynamic array section of the second adjoining pair of dynamic array sections and an entirety of a second boundary segment of a second dynamic array section of the second adjoining pair of dynamic array sections. 38. An integrated circuit device as recited in claim 32, wherein the first interconnect levels of the second adjoining pair of dynamic array sections further include one or more continuous first interconnect linear conductive segments that extend lengthwise in the second direction through the first interconnect level manufacturing assurance halo portions so as to extend continuously between the second adjoining pair of dynamic array sections. 39. An integrated circuit device as recited in claim 32, wherein each of the second adjoining pair of dynamic array sections is defined by a plurality of outer peripheral boundary segments extending in the second direction, and wherein the first interconnect level of at least one of the second adjoining pair of dynamic array sections includes an outermost first interconnect linear conductive segment formed to overlap one of the plurality of outer peripheral boundary segments extending in the second direction. 40. An integrated circuit device as recited in claim 32, wherein each of the plurality of dynamic array sections includes a respective second interconnect level that forms a portion of an overall second interconnect level of the integrated circuit device, wherein each of the plurality of dynamic array sections includes a number of second interconnect linear conductive segments formed within its second interconnect level, wherein the number of second interconnect linear conductive segments are formed in a parallel manner to extend lengthwise in the first direction, and wherein some of the number of second interconnect linear conductive segments within the second interconnect levels of the first adjoining pair of dynamic array sections are co-aligned in the first direction and separated by a second interconnect end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections. 41. An integrated circuit device as recited in claim 40, wherein each of the first adjoining pair of dynamic array sections is defined such that a respective second interconnect level manufacturing assurance halo portion extends in the first direction away from its co-located portion of outer peripheral boundary segment toward the other of the first adjoining pair of dynamic array sections, wherein each second interconnect end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections is sized to ensure that each second interconnect level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of any portion of the co-aligned second interconnect linear conductive segments. 42. An integrated circuit device as recited in claim 40, wherein the second interconnect levels of the first adjoining pair of dynamic array sections further include one or more continuous second interconnect linear conductive segments that extend lengthwise in the first direction through the second interconnect level manufacturing assurance halo portions so as to extend continuously between the first adjoining pair of dynamic array sections. 43. An integrated circuit device as recited in claim 40, wherein each of the first adjoining pair of dynamic array sections is defined by a plurality of outer peripheral boundary segments extending in the first direction, and wherein the second interconnect level of at least one of the first adjoining pair of dynamic array sections includes an outermost second interconnect linear conductive segment formed to overlap one of the plurality of outer peripheral boundary segments extending in the first direction.
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