초록 ▼

Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general

Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions.

대표청구항 ▼

1. A machine implemented method comprising: determining a state of an instruction queue of a subsystem of a data processing system; andsending a message about the state of the instruction queue to a processing unit of the data processing system in order to cause power to be reduced in the subsystem,

1. A machine implemented method comprising: determining a state of an instruction queue of a subsystem of a data processing system; andsending a message about the state of the instruction queue to a processing unit of the data processing system in order to cause power to be reduced in the subsystem, wherein power is reduced when the state of the instruction queue has instructions for only future events or actions, wherein time values of the future events or actions scheduled to be performed by the subsystem are adjusted at run-time by a latency value based on a power-up latency associated with the subsystem. 2. The machine implemented method of claim 1, wherein determining the state of the instruction queue of the subsystem further comprises: creating a list of future events or actions based on time values at which the future events or actions are scheduled to be performed by the subsystem. 3. The machine implemented method of claim 2, wherein the time values of the future events or actions scheduled to be performed by the subsystem are adjusted at run-time via a method comprising: monitoring the time to power up the subsystem to determine the power-up latency associated with the subsystem, andadjusting time values of the future events or actions based on the monitoring. 4. The machine implemented method of claim 3, wherein the power-up latency associated with the subsystem is a fixed value. 5. The machine implemented method of claim 3, wherein the power-up latency associated with a first subsystem differs from the power-up latency associated with a second subsystem. 6. The machine implemented method of claim 3, wherein the adjusted time values for the future events or actions to be performed by the subsystem are the difference between the scheduled time for the corresponding future event or action and the latency value. 7. The machine implemented method of claim 6, wherein power is reduced when the state of instructions queue has instructions for only future events or actions that are associated with adjusted time values exceeding zero. 8. A non-transitory machine-readable medium containing executable program instructions which cause a data processing system to perform a method comprising: determining a state of an instruction queue of a subsystem of the data processing system; andsending a message about the state of the instruction queue to a processing unit of the data processing system in order to cause power to be reduced in the subsystem, wherein power is reduced when the state of the instruction queue has instructions for only future events or actions, wherein time values of the future events or actions scheduled to be performed by the subsystem are adjusted at run-time by a latency value based on a power-up latency associated with the subsystem. 9. The non-transitory machine-readable medium of claim 8, wherein determining the state of the instruction queue of the subsystem further comprises: creating a list of future events or actions based on time values at which the future events or actions are scheduled to be performed by the subsystem. 10. The non-transitory machine-readable medium of claim 9, wherein the time values of the future events or actions scheduled to be performed by the subsystem are adjusted via operations comprising: monitoring the time to power up the subsystem to determine the power-up latency associated with the subsystem, andadjusting time values of the future events or actions based on the monitoring. 11. The non-transitory machine-readable medium of claim 10, wherein the power-up latency associated with the subsystem is a fixed value. 12. The non-transitory machine-readable medium of claim 10, wherein the power-up latency associated with a first subsystem differs from the power-up latency associated with a second subsystem. 13. The non-transitory machine-readable medium of claim 10, wherein the adjusted time values for the future events or actions to be performed by the subsystem are the difference between the scheduled time for a corresponding future event or action and the latency value. 14. The non-transitory machine-readable medium of claim 13, wherein power is reduced when the state of instructions queue has instructions for only future events or actions that are associated with adjusted time values exceeding zero. 15. A data processing system comprising: means for determining a state of an instruction queue of a subsystem of the data processing system; andmeans for sending a message about the state of the instruction queue to a processing unit of the data processing system in order to cause power to be reduced in the subsystem, wherein power is reduced when the state of the instruction queue has instructions for only future events or actions, wherein time values of the future events or actions scheduled to be performed by the subsystem are adjusted at run-time by a latency value based on a power-up latency associated with the subsystem. 16. The data processing system of claim 15, wherein the means for determining the state of the instruction queue of the subsystem further comprises: creating a list of future events or actions based on time values at which the future events or actions are scheduled to be performed by the subsystem. 17. The data processing system of claim 16, wherein the time values of future events or actions scheduled to be performed by the subsystem are adjusted via a method comprising: monitoring the time to power up the subsystem to determine the power-up latency associated with the subsystem, andadjusting time values of the future events or actions based on the monitoring. 18. The data processing system of claim 17, wherein the power-up latency associated with the subsystem is a fixed value. 19. The data processing system of claim 17, wherein the power-up latency associated with a first subsystem differs from the power-up latency associated with a second subsystem. 20. The data processing system of claim 17, wherein the adjusted time values for the future events or actions to be performed by the subsystem are the difference between the scheduled time for a corresponding future event or action and the latency value. 21. The data processing system of claim 20, wherein power is reduced when the state of instructions queue has instructions for only future events or actions that are associated with adjusted time values exceeding zero.