최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0292440 (2008-11-19) |
등록번호 | US-8767756 (2014-07-01) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 2 인용 특허 : 575 |
A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coor
A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive us used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.
1. A switch on a chip providing Fibre Channel switching comprising: a plurality of switch ports, at least one of the switch ports configured to couple to at least one Fibre Channel node and communicate with the Fibre Channel node using Fibre Channel signaling;a serializer/deserializer (SERDES) circu
1. A switch on a chip providing Fibre Channel switching comprising: a plurality of switch ports, at least one of the switch ports configured to couple to at least one Fibre Channel node and communicate with the Fibre Channel node using Fibre Channel signaling;a serializer/deserializer (SERDES) circuitry coupled to the at least one switch port, the SERDES including a transmission terminal and a receive terminal, wherein the SERDES circuitry is configured to receive serial data and de-multiplex the serial data into aligned characters and recover a receive clock from the data, and multiplex outgoing characters into a transmit data stream;an elasticity buffer memory coupled to the at least one switch port, the elasticity buffer memory configured to compensate for differences between a receive data rate and a transmit data rate on the at least one switch port;a crossbar switch coupled to the at least one switch port, wherein the crossbar switch is configured to selectively couple switch ports on the switch to pass a received Fibre Channel data frame between switch ports on the switch and to direct communications to a second switch when a switch port is remote;a memory including a routing table coupled to the at least one switch port that includes mapping between addresses of nodes and their associated switching ports, wherein the routing table determines a location of a destination node for routing Fibre Channel data frames including whether the destination node is local or remote on the second switch; anda management logic residing on the switch that is configured to provide fairness of access to destination nodes based on attempts to establish communication with the destination node. 2. The switch of claim 1, wherein the location determined by the routing table is at least one of: on a local Fibre Channel Arbitrated Loop, on a switch port local to the switch, and on the second switch. 3. The switch of claim 1, wherein the switch port is configured to receive an open (OPN) primitive including an Arbitrated Loop Physical Address (ALPA) of the destination node and access the memory using the ALPA to enable switching of data to the destination node. 4. The switch of claim 1, further comprising a JTAG circuit residing on the switch for testing. 5. The switch of claim 1, further comprising a microprocessor coupled to the crossbar switch to perform functions related to configuring the switch. 6. The switch of claim 1, further comprising a multiplexed bus for communicating with the second switch, wherein a virtual channel is established for each data flow allowing multiple data flows to be sent and received by the switch on the multiplexed bus, wherein channels for communication on the multiplexed bus include data channels and at least one channel dedicated to other uses. 7. The switch of claim 1, wherein the management logic provides priority levels for access to destination nodes, where priority levels for requests are escalated based on a number of consecutive denials. 8. The switch of claim 7, wherein a request is assigned a priority level and the priority level is temporarily adjusted to high priority status. 9. The switch of claim 1, further comprising a first-in first-out (FIFO) buffer for managing priority level requests for the at least one switch port. 10. The switch of claim 1, wherein the management logic changes settings of the switch to allow the switch to change from a hub mode to a switch mode. 11. The switch of claim 1, wherein flow control is used to hold back data from being transmitted until the switch is ready to transmit the data to the destination node and wherein primitive messaging is used to indicate when to hold back and when to transmit data frames. 12. The switch of claim 1, wherein the routing table is built using a active discovery process. 13. The switch of claim 1, further comprising a connection to a data path to a second switch with a remote switch port, wherein the data path is used to send Fibre Channel data frames to the remote switch port. 14. The switch of claim 13, wherein the data path to a second switch includes channels for the transmission of data from multiple switch ports. 15. The switch of claim 1, further comprising: a transmitting unit of the at least one switch port for forwarding the open primitive (OPN) to the destination node, when control of the FCAL net is won following an arbitration for the FCAL net; anda receiving unit of the at least one switch port configured to receive an Receive Ready (RRDY) primitive or a Close (CLS) primitive from the destination node and transmitting the primitive to the source node through a channel,wherein the switch continues to pass data frames and primitives between the source node and the destination node and using Fibre Channel primitives to provide flow control to indicate when to hold back and when to transmit data frames, until a CLS primitive is transmitted by either the source node or the destination node, and then closing the channel and relinquishing control of the FCAL net coupled to the switch port. 16. A method of Fibre Channel switching on a switch on a chip, the method comprising: communicating from a switch port on the switch using Fibre Channel signaling to at least one Fibre Channel node;receiving serial data at serializer/deserializer (SERDES) circuitry coupled to the at least one switch port and de-multiplexing the serial data into aligned characters and recovering a receive clock from the data;retiming data rates using an elasticity buffer memory to compensate for differences between a receive data and a transmit data rate;switching selectively to pass a received Fibre Channel data frame between switch ports on the switch and to direct communications to a second switch when a switch port is remote;determining a location of a destination node for routing Fibre Channel data frames including whether the destination node is local or remote on the second switch by accessing a routing table that includes mapping between addresses of nodes and their associated switching ports; andproviding fairness of access to destination nodes based on attempts to establish communication with the destination node using a management logic residing on the switch. 17. The method of claim 16, further comprising providing fairness of access to the switch on an individual port level to ensure a fraction of switch bandwidth is available. 18. The method of claim 16, further comprising: arbitrating for control of a second FCAL net coupled to a second port;forwarding the OPN to the destination node when control of the second FCAL net is won following the arbitration;receiving a Receive Ready (RRDY) primitive or a Close (CLS) primitive from the destination node and transmitting the primitive to the source node through the channel; andcontinuing to pass data frames and primitives between the source node and destination node and using Fibre Channel primitive messaging to provide flow control to indicate when to hold back and when to transmit data frames, until a CLS primitive is transmitted by either the source node or the destination node, and then closing the channel and relinquishing control of the FCAL net coupled to the second port. 19. The method of claim 16, wherein accessing the routing table includes determining which of the plurality of ports a destination node identified in the OPN is coupled to and enable switching of data to the destination node. 20. The method of claim 16, further comprising providing testing information from a JTAG circuit residing on the switch. 21. The method of claim 16, further comprising configuring the switch using a microprocessor. 22. The method of claim 16, further comprising: communicating with a second switch using a multiplexed bus; andestablishing a virtual channel for each data flow allowing multiple data flows to be sent and received by the switch on the multiplexed bus, wherein channels for communication on the multiplexed bus include data channels and at least one channel dedicated to other uses.
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