IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0493738
(2012-06-11)
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등록번호 |
US-8769248
(2014-07-01)
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발명자
/ 주소 |
- Hansen, Craig
- Moussouris, John
- Massalin, Alexia
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출원인 / 주소 |
- Microunity Systems Engineering, Inc.
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대리인 / 주소 |
McDermott Will & Emery LLP
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인용정보 |
피인용 횟수 :
1 인용 특허 :
113 |
초록
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Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capab
Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.
대표청구항
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1. A programmable processor comprising: an instruction path and a data path;a register file having at least a source register and a result register coupled to the data path; andan execution unit coupled to the instruction path and the data path operable to decode and execute group instructions recei
1. A programmable processor comprising: an instruction path and a data path;a register file having at least a source register and a result register coupled to the data path; andan execution unit coupled to the instruction path and the data path operable to decode and execute group instructions received from the instruction path, and on an instruction-by-instniction basis dynamically partition data from the source register into multiple source floating-point data elements each having a source precision, and wherein:in response to decoding a single group floating-point instruction indicating (i) the source register, (ii) the result register, and (iii) the source precision and a result precision, the result precision being a factor of two different than the source precision,the execution unit operates to (a) read the multiple source floating-point data elements from the source register, (b) convert each of the multiple source floating-point data elements to the result precision, thereby forming each of the multiple result floating-point data elements, and (c) catenate the multiple result floating-point data elements in the result register. 2. A programmable processor comprising: an instruction path and a data path;a register file having at least a source register and a result register coupled to the data path; andan execution unit coupled to the instruction path and the data path operable to decode and execute group instructions received from the instruction path, and on an instruction-by-instruction basis dynamically partition data from the source register into multiple source floating-point data elements each having a source precision, and wherein:in response to decoding a single group floating-point instruction indicating (i) the source register, (ii) the result register, and (iii) the source precision and a result precision, the result precision being twice the source precision,the execution unit operates to (a) read the multiple source floating-point data elements from the source register, (b) convert each of the multiple source floating-point data elements to the result precision, thereby forming each of the multiple result floating-point data elements, and (c) catenate the multiple result floating-point data elements in the result register. 3. The programmable processor of claim 2, wherein the source floating-point data elements and the result floating-point data elements have separate fields for a sign value, an exponent and a significand. 4. The programmable processor of claim 2, wherein the result precision is 32-bit precision. 5. The programmable processor of claim 2, wherein the result precision is 64-bit precision. 6. A programmable processor comprising: an instruction path and a data path;a register file having at least a source register and a result register coupled to the data path; andan execution unit coupled to the instruction path and the data path operable to decode and execute group instructions received from the instruction path, and on an instruction-by-instruction basis dynamically partition data from the source register into multiple source floating-point data elements each having a source precision, and wherein:in response to decoding a single group floating-point instruction indicating specifying (i) the source register, (ii) the result register, and (iii) the source precision and a result precision, the result precision being one-half the source precision,the execution unit operates to (a) read the multiple source floating-point data elements from the source register, (b) convert each of the multiple source floating-point data elements to the result precision, thereby forming each of the multiple result floating-point data elements, and (c) catenate the multiple result floating-point data elements in the result register. 7. The programmable processor of claim 6, wherein the source floating-point data elements and the result floating-point data elements have separate fields for a sign value, an exponent and a significand. 8. The programmable processor of claim 6, wherein the result precision is 16-bit precision. 9. The programmable processor of claim 6, wherein the result precision is 32-bit precision. 10. The programmable processor of claim 6, wherein step (b) comprises rounding each source floating-point data element using one of a plurality of rounding options. 11. The programmable processor of claim 10, wherein the single group floating-point instruction further specifies the rounding option. 12. A system comprising: a memory for storing instructions and data;a programmable processor coupled to the memory, the programmable processor including:an instruction path and a data path;a register file having at least a source register and a result register coupled to the data path; andan execution unit coupled to the instruction path and the data path operable to decode and execute group instructions received from the instruction path, and on an instruction-by-instruction basis dynamically partition data from the source register into multiple source floating-point data elements each having a source precision, and wherein:in response to decoding a single group floating-point instruction indicating (i) the source register, (ii) the result register, and (iii) the source precision and a result precision, the result precision being a factor of two different than the source precision,the execution unit operates to (a) read the multiple source floating-point data elements from the source register, (b) convert each of the multiple source floating-point data elements to the result precision, thereby forming each of the multiple result floating-point data elements, and (c) catenate the multiple result floating-point data elements in the result register. 13. A system comprising: a memory for storing instructions and data;a programmable processor coupled to the memory, the programmable processor including:an instruction path and a data path;a register file having at least a source register and a result register coupled to the data path; andan execution unit coupled to the instruction path and the data path operable to decode and execute group instructions received from the instruction path, and on an instruction-by-instruction basis dynamically partition data from the source register into multiple source floating-point data elements each having a source precision, and wherein:in response to decoding a single group floating-point instruction indicating (i) the source register, (ii) the result register, and (iii) the source precision and a result precision, the result precision being twice the source precision,the execution unit operates to (a) read the multiple source floating-point data elements from the source register, (b) convert each of the multiple source floating-point data elements to the result precision, thereby forming each of the multiple result floating-point data elements, and (c) catenate the multiple result floating-point data elements in the result register. 14. The system of claim 13, wherein the source floating-point data elements and the result floating-point data elements have separate fields for a sign value, an exponent and a significand. 15. The system of claim 13, wherein the result precision is 16-bit precision. 16. The system of claim 13, wherein the result precision is 32-bit precision. 17. The system of claim 13, wherein step (b) comprises rounding each source floating-point data element using one of a plurality of rounding options. 18. The system of claim 17, wherein the single group floating-point instruction further specifies the rounding option. 19. A system comprising: a memory for storing instructions and data;a programmable processor coupled to the memory, the programmable processor including:an instruction path and a data path;a register file having at least a source register and a result register coupled to the data path; andan execution unit coupled to the instruction path and the data path operable to decode and execute group instructions received from the instruction path, and on an instruction-by-instruction basis dynamically partition data from the source register into multiple source floating-point data elements each having a source precision, and wherein:in response to decoding a single group floating-point instruction indicating (i) the source register, (ii) the result register, and (iii) the source precision and a result precision, the result precision being one-half the source precision,the execution unit operates to (a) read the multiple source floating-point data elements from the source register, (b) convert each of the multiple source floating-point data elements to the result precision, thereby forming each of the multiple result floating-point data elements, and (c) catenate the multiple result floating-point data elements in the result register. 20. The system of claim 19, wherein the source floating-point data elements and the result floating-point data elements have separate fields for a sign value, an exponent and a significand. 21. The system of claim 19, wherein the result precision is 16-bit precision. 22. The system of claim 19, wherein the result precision is 32-bit precision. 23. The system of claim 19, wherein step (b) comprises rounding each source floating-point data element using one of a plurality of rounding options. 24. The system of claim 23, wherein the single group floating-point instruction further specifies the rounding option.
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