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System and apparatus for group floating-point inflate and deflate operations

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/302
출원번호 US-0493738 (2012-06-11)
등록번호 US-8769248 (2014-07-01)
발명자 / 주소
  • Hansen, Craig
  • Moussouris, John
  • Massalin, Alexia
출원인 / 주소
  • Microunity Systems Engineering, Inc.
대리인 / 주소
    McDermott Will & Emery LLP
인용정보 피인용 횟수 : 1  인용 특허 : 113

초록

Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capab

대표청구항

1. A programmable processor comprising: an instruction path and a data path;a register file having at least a source register and a result register coupled to the data path; andan execution unit coupled to the instruction path and the data path operable to decode and execute group instructions recei

이 특허에 인용된 특허 (113)

  1. Garcia ; Jr. Serafin J. E. (Boynton Beach FL) Gatson Michael S. (Boca Raton FL) Hoch Gary B. (Coral Springs FL) Stelzer Eric H. (Boca Raton FL) Williams Donald G. (Delray Beach FL), Adapters with descriptor queue management capability.
  2. Taaffe James L. (Arlington MA) Kaldis Maria (Boston MA), Apparatus and method for processing and displaying images in a digital procesor based system.
  3. Jouppi Norman P. (Palo Alto CA), Apparatus and method for single operand register array for vector and scalar data processing operations.
  4. Crawford John H. ; Choudhury Mustafiz R., Apparatus and method for swapping the byte order of a data item to effectuate memory format conversion.
  5. Lin, Derrick Chu; Minocha, Punit; Peleg, Alexander D.; Yaari, Yaakov; Mittal, Millind; Mennemeier, Larry M.; Eitan, Benny, Apparatus for performing packed shift operations.
  6. Balmer Keith (Bedford TX GB2) Gove Robert J. (Plano TX) Robertson Iain (Bedfordshire TX GB2) Guttag Karl M. (Sugar Land TX) Ing-Simmons Nicholas (Huntingdon GB2), Architecture of transfer processor.
  7. Balmer Keith (Bedford GB2) Ing-Simmons Nicholas (Huntingdon GB2) Guttag Karl M. (Missouri City TX) Gove Robert J. (Plano TX) Golston Jeremiah E. (Sugar Land TX) Read Christopher J. (Houston TX) Polan, Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section.
  8. Hirose Kenji (Hitachi JPX) Bandoh Tadaaki (Ibaraki JPX) Matsumoto Hidekazu (Hitachi JPX) Yamaguchi Shinichiro (Hitachi JPX) Hirayama Hirokazu (Hitachi JPX) Nakanishi Hiroaki (Hitachi JPX), Bit slice multiplication circuit.
  9. Kohn Leslie D. (San Jose CA), Bus apparatus having hold registers for parallel processing in a microprocessor.
  10. Schwartz Martin J. (Worcester MA) Howes H. Frank (Fayville MA) Edry Richard J. (Ashland MA), Byte addressable memory for variable length instructions and data.
  11. Sachs Howard G. (Los Altos CA) Cho James Y. (Los Gatos CA), Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to.
  12. Talgam Yoav (Tel-Aviv TX ILX) Klingshirn James A. (Austin TX) Gullette James B. (Austin TX), Cache which provides status information.
  13. Baier Alfred (Eckental DEX) Schuck Johannes (Rothenbach/Peg. DEX) Weinsziehr Dirk (Schnaittach DEX), Circuit arrangement for forming the sum of products.
  14. Gill Michael C. (Dallas TX) Darley Henry M. (Plano TX) Chiu Edison H. (Richardson TX) Niehaus Jeffrey A. (Dallas TX), Circuitry for transferring data from a data bus and temporary register into a plurality of input registers on clock edge.
  15. Cray ; Jr. ; Seymour R., Computer vector register processing.
  16. Nakayama Yozo (Yokohama JPX) Kubo Masahito (Sagamihara JPX) Yawata Yuuichi (Chigasaki JPX), Condition code producing system.
  17. Parks Terry J. (Round Rock TX) Jeffries Kenneth L. (Leander TX) Jones Craig S. (Austin TX), Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by.
  18. Finnila Charles A. (Los Angeles CA), Cooperative-word linear array parallel processor.
  19. Catt Ivor (“Hartspring” ; 17 King Harry Lane St. Albans ; Hertfordshire GB2), Data processing apparatus operative on data passing along a serial, segmented store.
  20. Rasala Edward (Westboro MA) Wallach Steven (Framingham MA) Alsing Carl J. (Hopkington MA) Holberger Kenneth D. (North Grafton MA) Holland Charles J. (Northboro MA) West Thomas (Boxboro MA) Guyer Jame, Data processing system.
  21. Cole Terence M. (Berkshire GB3) Poskitt Geoffrey (Surrey GB3), Data processing system with cache memory addressable by virtual and physical address.
  22. Biggs Terry L. (Dripping Springs TX) Lagana Antonio A. (Austin TX), Data processor having a cache memory capable of being used as a linear ram bank.
  23. Gergen Joseph P. (Austin TX) Percosan Peter A. (Austin TX), Data processor with an integer multiplication function on a fractional multiplier.
  24. Kobayashi Souichi (Itami JPX) Saito Yuichi (Itami JPX), Data processor with bus-sizing function.
  25. Murakami Tokumichi (Kanagawa JPX) Kinjo Naoto (Kanagawa JPX), Digital signal processor with high speed multiplier means for double data input.
  26. Sone Takashi (Tokyo JPX) Sato Jun (Musashino JPX), Drawing processor including arithmetical unit for improved superposed picture display.
  27. Ing-Simmons Nicholas K. (Oakley TX GB2) Guttag Karl M. (Missouri City TX) Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2), Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode.
  28. Patti Michael F. (Plainsboro NJ) Fedele Nicola J. (Kingston NJ) Harney Kevin (Brooklyn NY) Simon Allen H. (Belle Mead NJ), Dual mode combining circuitry.
  29. Choudhury Abhijit K. (Scotch Plains NJ) Hahne Ellen L. (Westfield NJ), Dynamic queue length thresholds in a shared memory ATM switch.
  30. Lee Ruby Bei-Loh (Los Altos Hills CA), Efficient selection and mixing of multiple sub-word items packed into two or more computer words.
  31. Cocanougher Daniel (Fort Worth TX) Montoye Robert K. (Austin TX) Nguyenphu Myhong (Austin TX) Runyon Stephen L. (Pflugerville TX), Floating point arithmetic two cycle data flow.
  32. Karp Alan H. (Sunnyvale CA) Markstein Peter (Woodside CA) Brzezinski Dennis (Sunnyvale CA), Floating point arithmetic unit using modified Newton-Raphson technique for division and square root.
  33. Birman Mark (Fremont CA) Chu George K. (Sunnyvale CA) Ware Fred A. (Los Altos Hills CA) Halim Selfia (Los Gatos CA), Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio.
  34. Elkind Bob (Gaston OR) Lessert Jay D. (Portland OR) Peterson James R. (Portland OR) Taylor Gregory F. (Portland OR), Floating point processor with internal free-running clock.
  35. Garcia Leslie C. (Poughkeepsie NY) Kollesar Nany H. (Poughkeepsie NY) Ling Huei (Chappaqua NY), Floating point unit for calculating a compound instruction A+B×C in two cycles.
  36. Ikumi Nobuyuki (Tokyo JPX), Functional dividable multiplier array circuit for multiplication of full words or simultaneous multiplication of two hal.
  37. Weng Lih-Jyh ; Shen Ba-Zhong ; Langer Diana, Galois field multiplier.
  38. Colwell Robert P. (Guilford CT) O\Donnell John (Guilford CT) Papworth David B. (Guilford CT) Rodman Paul K. (Madison CT), Hierarchical priority branch handling for parallel execution in a parallel processor.
  39. Caulk ; Jr. Robert L. (Pleasantor CA) Desai Sanjay M. (San Jose CA) Patel Jay P. (Union City CA), High performance graphics applications controller.
  40. Barnett, Howard S.; Cochran, Michael J.; Poland, Sid, High speed processor.
  41. New Bernard J. (Los Gatos CA) Flaherty Timothy J. (Santa Clara CA), High throughput extended-precision multiplier.
  42. Hiller John (New York NY) Johnsen Howard (Granite Spring NY) Mason John (Ramsey NJ) Mulhearn Brian (Paterson NJ) Petzinger John (Oakland NJ) Rosal Joseph (Bronx NY) Satta John (White Plains NY) Shurk, Highly parallel computer architecture employing crossbar switch with selectable pipeline delay.
  43. Fijany Amir (Sherman Oaks CA) Bejczy Antal K. (Pasadena CA), Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having r.
  44. Sites Richard L. (Boylston MA) Witek Richard T. (Littleton MA), In-register data manipulation using data shift in reduced instruction set processor.
  45. Coscarella Anthony (Woodstock NY) Sachs Martin W. (Westport CT) Temple Joseph (Hurley NY), Indirect addressing of channels via logical channel groups.
  46. Nishida Syuji,JPX ; Suetake Seiji,JPX ; Kamijo Shunsuke,JPX ; Furuya Kenji,JPX, Information processing device with decision circuits and partitioned address areas.
  47. Blahut Donald E. (Holmdel NJ) Szurkowski Edward S. (Maplewood NJ), Integrated television services system.
  48. Hesson James H. (Boise ID), Machine method to perform newton iterations for reciprocal square roots.
  49. Intrater Gideon (Tel-Aviv ILX) Oz Oved (Cfar Saba ILX) Tsadik Meir (Hod Hasharon ILX), Mechanism for handling non-maskable interrupt requests received from different sources.
  50. Watanabe Tadashi (Tokyo JPX), Memory arrangement operable as a cache and a local memory.
  51. Phelps Andrew E. (Eau claire WI) Beard Douglas R. (Eleva WI) Woodsmansee Michael A. (Eau Claire WI), Method and apparatus for a special purpose arithmetic boolean unit.
  52. Kahle Brewster A. (Somerville MA) Douglas David C. (Boston MA) Vasilevsky Alexander (Watertown MA) Christman David P. (Newport VT) Yang Shaw W. (Waltham MA) Crouch Kenneth W. (Cambridge MA), Method and apparatus for interfacing bit-serial parallel processors to a coprocessor.
  53. Baum Allen J. (Palo Alto CA), Method and apparatus for multi-gauge computation.
  54. Webb ; Jr. David A. (Berlin MA) Hetherington Ricky C. (Northboro MA) Murray John E. (Acton MA) Fossum Tryggve (Northboro MA) Manley Dwight P. (Holliston MA), Method and apparatus for ordering and queueing multiple memory requests.
  55. Briggs Willard S. (Carrollton TX) Brightman Thomas B. (Plano TX) Matula David W. (Dallas TX), Method and apparatus for performing the square root function using a rectangular aspect ratio multiplier.
  56. Guineau ; III William J. (Nashua NH), Method and apparatus for processing input/output commands in a storage system having a command queue.
  57. Pearson William C. ; Ogilvie Clarence R., Method and system for efficiently multiplying signed and unsigned variable width operands.
  58. DiNicola Paul D. (Hurley NY) Kantz Joseph (Saugerties NY) Rahim Omar M. (Kingston NY) Rice David A. (New Paltz NY) Ruddick Edward M. (Woodstock NY), Method and system for processing graphics data streams utilizing scalable processing nodes.
  59. Turkowski Kenneth E. (Palo Alto CA), Method and system for reordering bytes in a data stream.
  60. Peleg Alexander (Haifa ILX) Yaari Yaakov (Haifa ILX) Mittal Millind (South San Francisco CA) Mennemeier Larry M. (Boulder Creek CA) Eitan Benny (Haifa ILX), Method for multiplying packed data.
  61. Kohn Leslie D. (San Jose CA), Method for parallel instruction execution in a computer.
  62. Sidwell Nathan Mackenzie,GBX ; Barnaby Catherine Louise,GBX, Method for transposing multi-bit matrix wherein first and last sub-string remains unchanged while intermediate sub-stri.
  63. Mennemeier Larry ; Peleg Alexander,ILX ; Dulong Carole ; Mittal Millind ; Eitan Benny,ILX ; Kowashi Eiichi,JPX, Method of sorting numbers to obtain maxima/minima values with ordering.
  64. Mennemeier Larry ; Peleg Alexander,ILX ; Dulong Carole ; Mittal Millind ; Eitan Benny,ILX ; Kowashi Eiichi,JPX, Method of sorting signed numbers and solving absolute differences using packed instructions.
  65. Ikumi Nobuyuki (Tokyo JPX), Microprocessor with a function for three-dimensional graphic processing.
  66. Cushing David E. (Chelmsford MA) Tague Steven A. (Billerica MA), Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands.
  67. Murakami Tokumichi (Kanagawa JPX), Motion vector calculation method using sequential minimum distortion calculations at different densities.
  68. Levy Bernardo Navarro (Ann Arbor MI) Lee David Chin-Chung (San Diego CA), Multi-microprocessing unit on a single semiconductor chip.
  69. Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD).
  70. Gove Robert J. (Plano TX) Guttag Karl M. (Missouri City TX) Balmer Keith (Bedfordshire GB2) Ing-Simmons Nicholas K. (Bedfordshire GB2), Multi-processor with crossbar link of processors and memories and method of operation.
  71. Narita Masahisa (Hitachi JPX) Kaziwara Hisashi (Hitachi JPX) Asai Takeshi (Hitachi JPX) Morinaga Shigeki (Hitachi JPX) Kida Hiroyuki (Kokubunji JPX) Watabe Mitsuru (Katsuta JPX) Nakamikawa Tetsuaki (, Multiplication, division and square root extraction apparatus.
  72. Shiraishi Mikio (Yokohama JPX), Multiplier capable of calculating double precision, single precision, inner product and multiplying complex.
  73. Hong, John Suk-Hyun, Multiplier capable of multiplication of large multiplicands and parallel multiplications of small multiplicands.
  74. Wong Kenneth J. (Anaheim CA) Davies Steven P. (Ontario CA), Multiplier circuit with selectively interconnected pipelined multipliers for selectively multiplication of fixed and flo.
  75. Simpson Richard (Carlton TX GBX) Oakland Erick D. (Zavalla TX) Barr Graham M. (Raunds GBX), Normalization method for floating point numbers.
  76. Absil Robert P. L. (West Deptford NJ) Angevine Philip J. (Woodbury NJ) Bundens Robert G. (Mullica Hill NJ) Herbst Joseph A. (Turnersville NJ), Octane improvement in catalytic cracking and cracking catalyst composition therefor.
  77. Gooding David N. (Endicott NY) Shimp Everett M. (Endwell NY), Parallel digital arithmetic device having a variable number of independent arithmetic zones of variable width and locati.
  78. Hinds Christopher N. (Austin TX) Fiene Eric V. (Austin TX) Marquette Daniel T. (Austin TX) Quintana Eric E. (Austin TX), Parallel method and apparatus for detecting and completing floating point operations involving special operands.
  79. Purcell Stephen C. ; Patwa Nital P., Partitioned adder tree supported by a multiplexer configuration.
  80. Grant Robert H. (Toronto CAX) Stoevhase Bent (Toronto CAX) Purohit Robin (Toronto CAX) Book David (Thornhill CAX), Path allocation system and method having double link list queues implemented with a digital signal processor (DSP) for a.
  81. Perlman Robert M. (San Jose CA) Sobel Prem (Sunnyvale CA) McMinn Brian D. (Austin TX) Thaden Robert C. (Austin TX) Tamura Glenn A. (Austin TX) Lynch Thomas W. (Austin TX) Vesgesna Raju (Austin TX), Pipelined floating point processing unit.
  82. Gonzalez-Lopez Jorge (Red Hook NY) Hempel Bruce C. (Tivoli NY) Liang Bob C. (West Hurley NY), Pipelined lighting model processing system for a graphics workstation\s shading function.
  83. Sit Hon P. (Fremont CA) Galbi David (Mountain View CA) Chan Alfred K. (San Jose CA), Prenormalization for a floating-point adder.
  84. Lin, Derrick Chu; Minocha, Punit; Peleg, Alexander D.; Yaari, Yaakov; Mittal, Millind; Mennemeier, Larry M.; Eitan, Benny; Chennupaty, Srinivas, Processor capable of executing packed shift operations.
  85. Thekkath,Radhika; Uhler,G. Michael; Ho,Ying wai; Harrell,Chandlee B., Processor having a compare extension of an instruction set architecture.
  86. Corcoran Gary T. (Fanwood NJ) Fairfield Robert C. (Randolph NJ), Processor having general registers with subdivisions addressable in instructions by register number and subdivision type.
  87. Mary Luc (Bures sur Yvette FRX) Barazesh Bahman (Paris FRX), Processor to carry out data processing in different modes and multiplication device suitable for such a processor.
  88. Chiarulli Donald M. (4724 Newcomb Dr. Baton Rouge LA 70808) Rudd W. G. (Dept. of Computer Science Oregon State University Corvallis OR 97331) Buell Duncan A. (1212 Chippenham Dr. Baton Rouge LA 70808, Processor utilizing reconfigurable process segments to accomodate data word length.
  89. Hansen,Craig; Moussouris,John, Programmable processor and system for partitioned floating-point multiply-add operation.
  90. Garg Sanjiv (Fremont CA) Lentz Derek J. (Los Gatos CA) Nguyen Le T. (Monte Sereno CA) Chen Sho L. (Saratoga CA), RISC microprocessor architecture implementing multiple typed register sets.
  91. Baron Nathan (Oranit ILX) Marino Paul (Kfar Saba ILX) Goren Avner (Ramat-Hasaron ILX) Melanmed-Cohen Eyal (Jerusalem ILX), Real time cache implemented by on-chip memory having standard and cache operating modes.
  92. Adkins John T. (San Antonio TX) Pogorzelski James S. (Georgetown TX) Wilson Jacqueline H. (Austin TX), Scalable schedules for serial communications controller in data processing systems.
  93. Desmonds Daniel J. (Roseville MN), Shift network for dual width operands.
  94. Nguyen Le Trong ; Song Seungyoon Peter ; Mohamed Moataz A. ; Park Heonchul ; Wong Roney Sau Don, Single-instruction-multiple-data processing using multiple banks of vector registers.
  95. Bindloss Keith M. ; Garey Kenneth E. ; Watson George A. ; Earle John, Space vector data path.
  96. Ibarguren,Inigo Lizarralde, Static pedalling fitness apparatus with lateral swinging.
  97. Purcell Stephen C. (Mountain View CA), Structure and method for embedding two small multipliers in a larger multiplier.
  98. Purcell Stephen C. (Mountain View CA), Structure and method for shifting and reordering a plurality of data bytes.
  99. Purcell Stephen C., Structure and method for signed multiplication using large multiplier having two embedded signed multipliers.
  100. Petrick Bruce, System and method for performing multiway branches using a visual instruction set.
  101. Stager Gary B. (Plano TX), System for accessing distributed memory by breaking each accepted access request into series of instructions by using se.
  102. Lenoski Daniel (Cupertino CA) Jordan Albert (Mountain View CA), System for cache space allocation using selective addressing.
  103. Webb ; Jr. David A. (Berlin MA) Fite David B. (Northboro MA) Hetherington Ricky C. (Northboro MA) McKeen Francis X. (Westboro MA) Firstenberg Mark A. (Maynard MA) Murray John E. (Acton MA) Manley Dwi, System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a vir.
  104. Jardine Robert L. (Cupertino CA), System for multiplexing prioritized virtual channels onto physical channels where higher priority virtual will pre-empt.
  105. Miura Masaharu (202 ; Hikariso ; 6-2-3 ; Higashi-cho ; Houya-shi ; Tokyo JPX) Kawasaki Shumpei (301 ; Koganeinishi-Pahkuhoumuzu ; 3-13-15 ; Nukuiminami-cho Koganei-shi ; Tokyo JPX), System for selectively masking operand portions for processing thereof.
  106. Michel Claude (Asnieres FRX) M\Rabet Noureddine (Pantin FRX), System for simultaneous transmission of data blocks or vectors between a memory and one or a number of data-processing u.
  107. Yung Robert ; Joy William N. ; Tremblay Marc, Temporary pipeline register file for a superpipelined superscalar processor.
  108. Jones Gardner D. (Raleigh NC) Larsen Larry D. (Raleigh NC) Esteban Daniel J. (Cagnes Sur Mer FRX), Three phased pipelined signal processor.
  109. Wang Yulun (Goleta CA) Srinivasan Partha (Goleta CA), Three-dimensional vector co-processor having I, J, and K register files and I, J, and K execution units.
  110. Ooi Yasushi (Tokyo JPX), Vector processor which can be formed by an integrated circuit of a small size.
  111. Schiffleger Alan J. (Chippewa Falls WI) Gupta Ram K. (Eau Claire WI) Hsiung Christopher C. (Eau Claire WI), Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift count.
  112. Wang Wen-Hann (Portland OR), Virtual access cache protection bits handling method and apparatus.
  113. Colwell Robert P. (Guilford CT) O\Donnell John (Guilford CT) Papworth David B. (Guilford CT) Rodman Paul K. (Madison CT), Virtual address table look aside buffer miss recovery method and apparatus.

이 특허를 인용한 특허 (1)

  1. Chakra, Al; Harpur, Liam; Rice, John, Collaboratively reconstituting tables.
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