초록 ▼

A high performance real-time turbo code system is proposed. The proposed system exploits cooperative coding architecture and a proper decoding scheduling to achieve low error rate within a constrained latency. Permutation schemes and hardware embodiments utilizing the cooperative coding are also sho

A high performance real-time turbo code system is proposed. The proposed system exploits cooperative coding architecture and a proper decoding scheduling to achieve low error rate within a constrained latency. Permutation schemes and hardware embodiments utilizing the cooperative coding are also shown. Various memory saving techniques are provided to reduce memory usage in both encoder and decoder. The proposed system is compatible with 3rd generation mobile standards and cost of designing new parts exclusively for the proposed system can be minimized. This invention can provide substantial coding and system capacity gains for real-time applications in a wireless environment.

대표청구항 ▼

1. A turbo code system comprising: an inter-sequence permutation turbo code decoder, the inter-sequence permutation turbo code decoder including: a scheduler pool including at least one scheduler configured to receive a codeword sequence;an a-posteriori probability decoder pool, including an a-poste

1. A turbo code system comprising: an inter-sequence permutation turbo code decoder, the inter-sequence permutation turbo code decoder including: a scheduler pool including at least one scheduler configured to receive a codeword sequence;an a-posteriori probability decoder pool, including an a-posteriori probability decoder configured to decode the codeword sequence in an a-posteriori probability decoding run;a memory pool to store sequences; andan inter-sequence permutation control unit pool having at least one inter-sequence permutation control unit, the at least one inter-sequence permutation control unit configured to use an inter-sequence permutation algorithm and interchange sequences with the memory pool, wherein the inter-sequence permutation algorithm is embedded in the inter-sequence permutation control unit to control inputting to the memory pool and outputting from the memory pool, andwherein the scheduler is configured to control operations of the a-posteriori probability decoder pool and control the a-posteriori probability decoding run of the received codeword sequence. 2. The turbo code system as claimed in claim 1, further comprising at least one pair of sequence permuter pools and at least on pair of sequence de-permuter pools, wherein the pair of sequence permuter pools and the pair of sequence de-permuter pools interchange sequences with the memory pool. 3. The turbo code system as claimed in claim 1, further comprising at least one adder and one subtractor. 4. The turbo code system as claimed in claim 1, further comprising at least one multiplier and one divider. 5. The turbo code system as claimed in claim 1, wherein the at least one scheduler is arranged as a ring type. 6. The turbo code system as claimed in claim 1, wherein the at least one scheduler is arranged in a star type. 7. The turbo code system as claimed in claim 6, further comprising a scheduler controller coupled to the at least one scheduler in the scheduler pool. 8. The turbo code system as claimed in claim 1, wherein the scheduler pool further comprises at least one decision maker configured to output a hard decoding output sequence. 9. The turbo code system as claimed in claim 1, wherein the inter-sequence permutation turbo code decoder further comprises a decoder index table storing information on relationship between necessity to perform a-posteriori probability decoding and codeword sequence numbers, the decoder index table coupled to the scheduler pool and configured to interchange information with the scheduler pool. 10. The turbo code system as claimed in claim 1, the scheduler pool coupled to at least one termination tester to perform a termination test. 11. The turbo code system as claimed in claim 1, further comprising an inter-sequence de-permutation control unit pool, the inter-sequence de-permutation control unit pool including at least one inter-sequence de-permutation control unit, the at least one inter-sequence de-permutation control unit using an inter-sequence de-permutation algorithm and interchanging sequences with the memory pool. 12. A turbo code system comprising: an inter-sequence permutation turbo code decoder configured to receive a pre-permutation codeword sequence output and a post-permutation codeword sequence output, the inter-sequence permutation turbo code decoder including: an a-posteriori probability decoder pool configured to decode the received pre-permutation codeword sequence output and the post-permutation codeword sequence output in an a-posteriori probability decoding run;a memory pool to store sequences;a scheduler pool including at least one scheduler, the at least one scheduler configured to provide and retrieve sequences to and from the a-posteriori probability decoder pool and the memory pool, wherein the scheduler is configured to control operations of the a-posteriori probability decoder pool and control the a-posteriori probability decoding run of the received pre-permutation codeword sequence output and post-permutation codeword sequence output;an inter-sequence permutation control unit pool having at least one inter-sequence permutation control unit, wherein an inter-sequence permutation algorithm is embedded in the inter-sequence permutation control unit to control inputting to the memory pool and outputting from the memory pool; andan inter-sequence de-permutation control unit pool having at least one inter-sequence de-permutation control unit, the at least one inter-sequence permutation control unit and the at least one inter-sequence de-permutation control unit configured to use the inter-sequence permutation algorithm and to interchange sequences with the memory pool. 13. The turbo code system as claimed in claim 12, wherein the at least one scheduler is arranged as a ring type. 14. The turbo code system as claimed in claim 12, wherein the at least one scheduler is arranged in a star type. 15. The turbo code system as claimed in claim 12, wherein the scheduler pool further comprises at least one decision maker configured to output a hard decoding output sequence. 16. The turbo code system as claimed in claim 12, the scheduler pool coupled to at least one termination tester to perform a termination test. 17. A turbo code system comprising: an inter-sequence permutation turbo code decoder configured to receive a pre-permutation codeword sequence output and a post-permutation codeword sequence output, the inter-sequence permutation turbo code decoder including: an a-posteriori probability decoder pool having at least one a-posteriori probability decoder, the at least one a-posteriori probability decoder configured to decode the received pre-permutation codeword sequence output and the post-permutation codeword sequence output;a memory pool to store sequences;a scheduler pool including at least one scheduler, the at least one scheduler configured to provide and retrieve sequences to and from the a-posteriori probability decoder pool and the memory pool, wherein the scheduler is configured to control operations of the a-posteriori probability decoder pool and control the a-posteriori probability decoding run of the received pre-permutation codeword sequence output and post-permutation codeword sequence output;a scheduler controller coupled to each scheduler in the scheduler pool to control the operation of the scheduler;an inter-sequence permutation control unit pool having at least one inter-sequence permutation control unit, wherein an inter-sequence permutation algorithm is embedded in the inter-sequence permutation control unit to control inputting to the memory pool and outputting from the memory pool; andan inter-sequence de-permutation control unit pool have at least one inter-sequence de-permutation control unit, the at least one inter-sequence permutation control unit and the at least one inter-sequence de-permutation control unit configured to use the inter-sequence permutation algorithm and to interchange sequences with the memory pool. 18. The turbo code system as claimed in claim 17, wherein the inter-sequence permutation turbo code decoder further comprises a decoder index table storing information on relationship between necessity to perform the a-posteriori probability decoding and codeword sequence numbers, the decoder index table coupled to the scheduler pool and configured to interchange information with the scheduler pool. 19. The turbo code system as claimed in claim 17, further comprising at least one pair of sequence permuter pools and sequence de-permuter pools, wherein the pair of sequence permuter pools and sequence de-permuter pools interchange sequences with the memory pool. 20. The turbo code system as claimed in claim 17, wherein the scheduler pool further comprises at least one decision maker configured to output a hard decoding output sequence.