Method for fabricating a field effect transistor, and field effect transistor
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/336
H01L-021/8234
출원번호
US-0559572
(2006-11-14)
등록번호
US-8772097
(2014-07-08)
우선권정보
DE-10 2005 054 219 (2005-11-14)
발명자
/ 주소
Giles, Luis-Felipe
Lau, Frank
Liebmann, Rainer
출원인 / 주소
Infineon Technologies AG
대리인 / 주소
Schiff Hardin LLP
인용정보
피인용 횟수 :
1인용 특허 :
3
초록▼
In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cav
In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed in the substrate at least below the channel region, and the micro-cavities are oxidized.
대표청구항▼
1. A method for fabricating a field effect transistor, comprising: forming a first source/drain region and a second source/drain region in a substrate;forming a channel region between the first source/drain region and the second source/drain region;forming a gate region on the channel region;forming
1. A method for fabricating a field effect transistor, comprising: forming a first source/drain region and a second source/drain region in a substrate;forming a channel region between the first source/drain region and the second source/drain region;forming a gate region on the channel region;forming micro-cavities in the substrate below the channel region and laterally between the first source/drain region and the second source/drain region;oxidizing the micro-cavities to form discontinuous, oxidized micro-cavities below the channel region and laterally between the first source/drain region and the second source/drain region; anddoping the first source/drain region and the second source/drain region after the micro-cavities are oxidized, to thereby form a field effect transistor comprising the discontinuous, oxidized micro-cavities below the channel region and laterally between the first source/drain region and the second source/drain region. 2. The method as claimed in claim 1, wherein the step of forming the micro-cavities comprises: forming micro-platelets in the substrate, andforming the micro-cavities from the micro-platelets. 3. The method as claimed in claim 2, wherein the micro-platelets are elongated along a plane parallel to the surface of the substrate. 4. The method as claimed in claim 2, wherein the step of forming the micro-cavities comprises implanting light ions into the substrate so that the micro-platelets are formed in the substrate. 5. The method as claimed in claim 2, wherein the step of forming the micro-cavities comprises thermally treating the substrate with the micro-platelets to form the micro-cavities. 6. The method as claimed in claim 5, wherein the step of thermally treating the substrate with the micro-platelets comprises heating the substrate to a temperature of between 600° C. and 800° C. 7. The method as claimed in claim 5, wherein the step of thermally treating the substrate with the micro-platelets comprises heating the substrate for a duration of between 10 minutes and 2 hours. 8. The method as claimed in claim 5, wherein the step of forming the micro-cavities further comprises thermally treating the substrate a second time to effect a ripening process of the micro-cavities. 9. The method as claimed in claim 8, wherein the step of thermally treating the substrate a second time comprises heating the substrate to a temperature between 1000° C. and 1300° C. 10. The method as claimed in claim 9, wherein the step of thermally treating the substrate a second time comprises heating the substrate for a duration of between 1 μs and 1 s. 11. The method as claimed in claim 1, wherein the step of forming the micro-cavities comprises implanting light ions into the substrate. 12. The method as claimed in claim 11, wherein the light ions are at least one of the types of light ions selected from the group consisting of H2+ ions, He+ ions, F+ ions, Ne+ ions, Cl+ ions, and Ar+ ions. 13. The method as claimed in claim 11, wherein the light ions are implanted with an implantation dose of between 1015 cm−2 and 4×1017 cm−2. 14. The method as claimed in claim 11, wherein the light ions used during the implantation have an energy of between 10 keV and 150 keV. 15. The method as claimed in claim 11, wherein the light ions are implanted using a mask. 16. The method as claimed in claim 1, wherein the step of oxidizing the micro-cavities comprises: oxidizing the micro-cavities via a high-temperature treatment; andintroducing oxygen into the micro-cavities. 17. The method as claimed in claim 16, wherein the step of oxidizing the micro-cavities via a high-temperature treatment comprises heating the substrate to a temperature of between 1000° C. and 1350° C. 18. The method as claimed in claim 17, wherein the step of oxidizing the micro-cavities via a high-temperature treatment comprises heating the substrate for a duration of between 30 minutes and 2 hours. 19. The method as claimed in claim 16, wherein the step of introducing oxygen into the micro-cavities comprises introducing oxygen into the micro-cavities by thermal indiffusing oxygen or by implanting oxygen. 20. The method as claimed in claim 1, wherein a silicon substrate is used as the substrate. 21. The method as claimed in claim 20, wherein a (100) silicon substrate or a (111) silicon substrate is used as the substrate. 22. The method as claimed in claim 20, wherein the step of oxidizing the micro-cavities results in a formation of silicon dioxide precipitates, which produce a tensile stress field. 23. The method as claimed in claim 1, wherein the field effect transistor is an n-MOS field effect transistor with an n-doped first source/drain region, an n-doped second source/drain region, and a p-doped channel region. 24. The method as claimed in claim 23, further comprising forming a nitride layer on at least one region selected from the group of regions consisting of a partial region of the first source/drain region, a partial region of the second source/drain region, and a partial region of the gate region. 25. A field effect transistor fabricated using the method of claim 1. 26. A method for fabricating a field effect transistor, comprising: forming a first and a second source/drain region in a substrate;forming a channel region between the first and the second source/drain region;forming a gate region on the channel region;forming micro-cavities in the substrate below the channel region by implanting light ions into the substrate region laterally between the first source/drain region and the second source/drain region;oxidizing the micro-cavities to form discontinuous, oxidized micro-cavities below the channel region and laterally between the first source/drain region and the second source/region; anddoping the first source/drain region and the second source/drain region after the micro-cavities are oxidized, to thereby form a field effect transistor comprising the discontinuous, oxidized micro-cavities below the channel region and laterally between the first source/drain region and the second source/drain region. 27. A method for fabricating a field effect transistor, comprising: forming a first and a second source/drain region in a substrate;forming a channel region between the first and the second source/drain region;forming a gate region on the channel region;forming micro-cavities in the substrate below the channel region and laterally between the first source/drain region and the second source/drain region;oxidizing the micro-cavities to form, below the channel region and laterally between the first source/drain region and the second source/drain region, discontinuous micro-cavities having silicon dioxide precipitates; anddoping the first source/drain region and the second source/drain region after the micro-cavities are oxidized, to thereby form a field effect transistor comprising the discontinuous, oxidized micro-cavities below the channel region and laterally between the first source/drain region and the second source/drain region,wherein a tensile stress field is produced at least in a partial region of the channel region.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (3)
Davari Bijan ; Sadana Devendra Kumar ; Shahidi Ghavam G. ; Tiwari Sandip, Patterned SOI regions in semiconductor chips.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.