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Integrated circuit package system employing mold flash prevention technology 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/31
출원번호 US-0536382 (2012-06-28)
등록번호 US-8772916 (2014-07-08)
발명자 / 주소
  • Jang, Ki Youn
  • Song, Sungmin
  • Bae, JoHyun
출원인 / 주소
  • Stats Chippac Ltd.
대리인 / 주소
    Ishimaru & Associates LLP
인용정보 피인용 횟수 : 0  인용 특허 : 35

초록

An integrated circuit package system that includes: a support structure including an electrical contact; a solder mask over the support structure, the solder mask including a solder mask flange, the solder mask flange directly on a support structure first surface; an integrated circuit over the supp

대표청구항

1. An integrated circuit package system comprising: a support structure including an electrical contact;a solder mask over the support structure, the solder mask including a solder mask flange, the solder mask flange directly on a support structure first surface;an integrated circuit over the suppor

이 특허에 인용된 특허 (35)

  1. Baird John (Scottsdale AZ) Knapp James H. (Gilbert AZ), Apparatus for encapsulating a semiconductor device.
  2. Thummel Steven G., Apparatus for encasing array packages.
  3. Yoneda Yoshihiro (Kawasaki JPX) Ozawa Takashi (Kawasaki JPX), BGA semiconductor device including a plurality of semiconductor chips located on upper and lower surfaces of a first sub.
  4. Weber, Patrick O., Chip package with molded underfill.
  5. Payne Robert L. ; Reiter Herbert, Face on face flip chip integration.
  6. Huang, Chien-Ping; Ho, Tzong-Da, Flash-preventing semiconductor package.
  7. Salatino, Matthew M.; Weber, Patrick O., Integrated circuit package including opening exposing portion of an IC.
  8. Corisis,David J.; Chong,Chin Hui; Lee,Choon Kuan, Metal core foldover package structures.
  9. Lee, Kian Chai; Tim, Teoh Bee Yong; M, Vijendran; Choong, Lien Wah, Method and apparatus for distributing mold material in a mold for packaging microelectronic devices.
  10. Thummel Steven G., Method for encasing array packages.
  11. Thummel, Steven G., Method for encasing array packages.
  12. Bolken Todd O. ; Peters David L. ; Tandy Patrick W. ; Cobbley Chad A., Method for fabricating semiconductor packages using mold tooling fixture with flash control cavities.
  13. Mitchell, Craig; Warner, Mike; Behlen, Jim, Method for making a semiconductor chip package.
  14. Ishida Yoshihiro (Tokorozawa JPX) Komatsu Katsuji (Kawagoe JPX) Mimura Seiichi (Kawagoe JPX) Takenouchi Kikuo (Higashimurayama JPX) Yabe Isao (Tokorozawa JPX) Ichikawa Shingo (Sayama JPX) Shimada Yos, Method of making a resin encapsulated pin grid array with integral heatsink.
  15. Vincent Lin TW; Chi Ming Chang TW, Method of making substrate for use in forming image sensor package.
  16. Barber Ivor G., Method of packaging integrated circuits.
  17. Salatino,Matthew M.; Weber,Patrick O., Methods and apparatus for making integrated circuit package including opening exposing portion of the IC.
  18. Tan,Cher Khng Victor; Lee,Choon Kuan; Lee,Kian Chai; Lim,Guek Har; Tay,Wuu Yean; Poh,Teck Huat; Poh,Cheng Pour, Methods for designing carrier substrates with raised terminals.
  19. Hundt, Michael J.; Zhou, Tiao, Mold with compensating base.
  20. Gallas William N., Packaging multiple dies on a ball grid array substrate.
  21. Takahashi,Yoshimi, Plastic semiconductor package having improved control of dimensions.
  22. Kohno Ryuji (Ibaraki JPX) Nishimura Asao (Ushiku JPX) Kitano Makoto (Tsuchiura JPX) Yaguchi Akihiro (Ibaraki JPX) Yoneda Nae (Ibaraki JPX), Plastic-molded-type semiconductor device.
  23. Daido, Yukiko, Printed wiring board for attachment to a socket connector, having recesses and conductive tabs.
  24. Campbell Jeffrey S. ; Holton James T., Process of molding an insert on a substrate.
  25. Sota Yoshiki (Tenri JPX), Resin sealing type semiconductor device having fixed inner leads.
  26. Waki Masaki (Sagamihara JPX) Kasai Junichi (Kawasaki JPX) Aoki Tsuyoshi (Sagamihara JPX) Honda Toshiyuki (Kawasaki JPX) Sato Hirotaka (Kawasaki JPX), Semiconductor device having a plurality of chips.
  27. Shin, Won Sun; Lee, Seon Goo; Chun, Do Sung; Jang, Tae Hoan; DiCaprio, Vincent D., Semiconductor package and method for fabricating the same.
  28. Chen,Yen Chun; Lin,Sun Zen; Chang,Chich Yuan, Semiconductor package with exposed heat sink and the heat sink thereof.
  29. Bolken, Todd O.; Peters, David L.; Tandy, Patrick W.; Cobbley, Chad A., Semiconductor package with molded flash.
  30. Kim,Sang Uk; Youn,Han Shin, Semiconductor packaging mold and method of manufacturing semiconductor package using the same.
  31. Kiritani, Mika, Semiconductor resin molding method.
  32. Takiar Hem P. (Fremont CA) Lin Peng-Cheng (Cupertino CA) Nguyen Luu T. (San Jose CA), Stacked multi-chip modules and method of manufacturing.
  33. Jichen Wu TW; Meng Ru Tsai TW; Nai Hua Yeh TW; Chen Pin Peng TW, Stacked structure of semiconductor means and method for manufacturing the same.
  34. James,Stephen L.; Williams,Vernon M., Standoffs for centralizing internals in packaging process.
  35. Huang Chien-Ping,TWX ; Ko Eric,TWX, Thermally enhanced quad flat non-lead package of semiconductor.
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