Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/48
H01L-023/52
H01L-029/40
출원번호
US-0287826
(2011-11-02)
등록번호
US-8779601
(2014-07-15)
발명자
/ 주소
Gan, Kah Wee
Huang, Yaohuang
Jin, Yonggang
출원인 / 주소
STMicroelectronics Pte Ltd
대리인 / 주소
Seed IP Law Group PLLC
인용정보
피인용 횟수 :
9인용 특허 :
44
초록▼
An eWLB package for 3D and PoP applications includes a redistribution layer on a support wafer. A semiconductor die is coupled to the redistribution layer, and solder balls are also positioned on the redistribution layer. The die and solder balls are encapsulated in a molding compound layer, which i
An eWLB package for 3D and PoP applications includes a redistribution layer on a support wafer. A semiconductor die is coupled to the redistribution layer, and solder balls are also positioned on the redistribution layer. The die and solder balls are encapsulated in a molding compound layer, which is planarized to expose top portions of the solder balls. A second redistribution layer is formed on the planarized surface of the molding compound layer. A ball grid array can be positioned on the second redistribution layer to couple the semiconductor package to a circuit board, or additional semiconductor dies can be added, each in a respective molding compound layer. The support wafer can act as an interposer, in which case it is processed to form TSVs in electrical contact with the first redistribution layer, and a redistribution layer is formed on the opposite side of the support substrate, as well.
대표청구항▼
1. A device, comprising: a support substrate having a front face and a back face;a first redistribution layer positioned on the front face of the support substrate, and having a first plurality of contact pads and a first plurality of electrical traces extending between respective pairs of the first
1. A device, comprising: a support substrate having a front face and a back face;a first redistribution layer positioned on the front face of the support substrate, and having a first plurality of contact pads and a first plurality of electrical traces extending between respective pairs of the first plurality of contact pads;a first molding compound layer positioned on the front face of the support substrate over the first redistribution layer;a first semiconductor die having a plurality of circuit pads positioned on a front face of the first die, the first semiconductor die being substantially embedded in the first molding compound layer, the first die being positioned with the front face facing the first redistribution layer, and having the circuit pads electrically coupled to a respective one of the first plurality of contact pads;a first plurality of solder balls substantially embedded in the first molding compound layer and positioned on the first redistribution layer on a respective one of the first plurality of contact pads, a portion of each of the first plurality of solder balls lying coplanar with a face of the first molding compound layer;a second redistribution layer positioned on the face of the first molding compound layer, the second redistribution layer including a second plurality of contact pads and a second plurality of electrical traces extending between respective pairs of the second plurality of contact pads, each of the first plurality of solder balls being electrically coupled to a respective one of the second plurality of electrical traces; anda plurality of through vias located in the support substrate, each of the through vias extending from the front face of the support substrate to the back of the support substrate, each of the through vias being in electrical contact with a respective one of the first plurality of electrical traces. 2. The device of claim 1, comprising a plurality of solder joints that electrically couple each of the circuit pads of the first semiconductor die to the respective one of the first plurality of contact pads of the first redistribution layer. 3. The device of claim 1, comprising a second plurality of solder balls, each positioned over and electrically coupled to one of the second plurality of contact pads. 4. The device of claim 3 wherein the second plurality of solder balls is arranged in a ball grid array configured to electrically couple the device to a circuit board. 5. The device of claim 4, comprising: a second molding compound layer positioned on the face of the first molding compound layer; anda second semiconductor die having a plurality of circuit pads positioned on a front face thereof, the second semiconductor die being substantially embedded in the second molding compound layer, each of the circuit pads of the second semiconductor die electrically coupled to a respective one of the second plurality of contact pads, each of the second plurality of solder balls being substantially embedded in the second molding compound layer with a back portion of each of the second plurality of solder balls lying coplanar with a face of the second molding compound layer. 6. The device of claim 1 wherein the support substrate is silicon. 7. A device comprising: a support substrate having a front and a back face;first redistribution layer positioned on the front face of the support substrate, and having a first plurality of contact pads and a first plurality of electrical traces extending between respective pairs of the first plurality of contact pads, wherein the first redistribution layer positioned includes a second plurality of contact pads and a second plurality of electrical traces;a first molding compound layer positioned on the front face of the support substrate over the first redistribution layer;a first semiconductor die having a plurality of circuit pads positioned on a front face of the first die, the first die being positioned with front face facing the first redistribution layer, and having the circuit pads electrically coupled to a respective one of the first plurality of contact pads;a first plurality of solder balls substantially embedded in the first molding compound layer and positioned on the first redistribution layer on a respective one of the first plurality of contact pads, a portion of each of the first plurality of solder balls lying coplanar with a face of the first molding compound layer;a second redistribution ;layer positioned on the face of the first molding compound layer, the second redistribution layer including a second plurality of contact pads and a second plurality of electrical traces extending between respective pairs of the second plurality of contact pads, each of the first plurality of solder balls being electrically coupled to a respective one of the second plurality of electrical traces;a plurality of through vias located in the support substrate, each of the through vias extending from the front face of the support substrate to the back of the support substrate, each of through vias being in electrical contact with a respective one of the first plurality of electrical tracers, each of the plurality of through vias electrically coupling one of the second plurality of electrical traces electrically coupling one of the second plurality of contact pads to a respective one of the plurality of through vias. 8. The device of claim 7, comprising a second plurality of solder balls, each of the solder balls positioned over and electrically coupled to one of the second plurality of contact pads. 9. The device of claim 8 wherein the second plurality of solder balls is arranged in a ball grid array configured to electrically couple the device to a circuit board. 10. The device of claim 7 wherein the support substrate is silicon.
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