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Power semiconductor devices having termination structures 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/78
출원번호 US-0878429 (2010-09-09)
등록번호 US-8786045 (2014-07-22)
발명자 / 주소
  • Challa, Ashok
  • Lee, Jaegil
  • Jung, Jinyoung
  • Jang, Hocheol
출원인 / 주소
  • Fairchild Semiconductor Corporation
인용정보 피인용 횟수 : 2  인용 특허 : 362

초록

In one general aspect, a termination structure can include a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type where the plurality of pillars define a plurality of concentric rings surrounding an ac

대표청구항

1. A termination structure, comprising: a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type, the plurality of pillars defining a plurality of concentric rings surrounding an active area of a semicon

이 특허에 인용된 특허 (362)

  1. Korec Jacek ; Bhalla Anup, Barrier accumulation-mode MOSFET.
  2. Baliga Bantval J. (Schenectady NY) Chang Hsueh-Rong (Scotia NY) Howell Edward K. (Simsbury CT), Bidirectional field effect semiconductor device and circuit.
  3. Schutten, Herman P.; Benjamin, James A.; Lade, Robert W., Bidirectional power FET with substrate-referenced shield.
  4. Williams Richard K., Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench.
  5. Laska Thomas,DEX ; Auerbach Franz,DEX ; Brunner Heinrich,DEX ; Porst Alfred,DEX ; Tihanyi Jenoe,DEX ; Miller Gerhard,DEX, Bipolar transistor which can be controlled by field effect and method for producing the same.
  6. Grebs, Thomas E.; Kocon, Christopher B.; Ridley, Sr., Rodney S.; Dolny, Gary M.; Kraft, Nathan Lawrence; Skurkey, Louise E., Buried gate-field termination structure.
  7. Henkles ; Walter H. (Putnam Valley NY) Hwang Wei (Armonk NY), Buried-sidewall-strap two transistor one capacitor trench cell.
  8. Carmello, Diego; Garilli, Marco; Fatutto, Pierluigi; Caccialupi, Letizia, Catalyst, process for its preparation, and its use in the synthesis of 1,2-dichloroethane.
  9. Erwin A. Hijzen NL; Raymond J.E. Hueting NL, Cellular trench-gate field-effect transistors.
  10. Grung Bernard L. (Minneapolis MN) Warner ; Jr. Raymond M. (Edina MN) Zipperian Thomas E. (St. Paul MN), Channel collector transistor.
  11. Ballantine Arne Watson ; Coolbaugh Douglas Duane ; Gilbert Jeffrey D., Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield.
  12. Singer Barry M. (New York NY) Jayaraman Rajsekhar (Cambridge MA), Combined bipolar-field effect transistor resurf devices.
  13. Dirk Ahlers DE; Frank Pfirsch DE, Compensation component and process for producing the compensation component.
  14. Williams Richard K. (Cupertino CA) Blanchard Richard A. (Los Altos CA), Complementary, isolated DMOS IC technology.
  15. Seki Yasukazu (Kanagawa JPX), Conductivity modulation buried gate trench type MOSFET.
  16. Nakagawa Akio (Hiratsuka JPX) Yamaguchi Yoshihiro (Urawa JPX) Watanabe Kiminori (Kawasaki JPX), Conductivity-modulation metal oxide field effect transistor with single gate structure.
  17. Murakami Susumu (Ibaraki JPX) Satou Yukimasa (Hitachi JPX) Narita Hiroshi (Katsuta JPX), Constant-voltage diode for over-voltage protection.
  18. Chatterjee Pallab K. (Richardson TX) Malhi Satwinder (Garland TX) Richardson William F. (Richardson TX), DRAM Cell with trench capacitor and vertical channel in substrate.
  19. Agahi Farid ; Hsu Louis L. ; Mandelman Jack A., DRAM cell having an annular signal transfer region.
  20. Wanlass Frank M., Damascene formation of borderless contact MOS transistors.
  21. Baliga Bantval Jayant (Raleigh NC) Thapar Naresh I. (Raleigh NC), Depleted base transistor with high forward voltage blocking capability.
  22. Fwu-Iuan Hshieh ; Koon Chong So ; Yan Man Tsui, Devices and methods for addressing optical edge effects in connection with etched trenches.
  23. Nagasu Masahiro,JPX ; Mori Mutsuhiro,JPX ; Kobayashi Hideo,JPX ; Sakano Junichi,JPX, Diode and power converting apparatus.
  24. Nishizawa Jun-ichi (Miyagi JPX) Kondoh Hisao (Osaka JPX), Double gate static induction thyristor.
  25. Sapp, Steven, Dual trench power MOSFET.
  26. Tihanyi Jenoe,DEX, Edge structure and drift region for a semiconductor component and production method.
  27. Jun Zeng ; Gary Mark Dolry ; Praveen MurAleedharan, Edge termination for silicon power devices.
  28. Hueting, Raymond J. E.; Hijzen, Erwin A.; In't Zandt, Michael A. A., Edge termination in MOS transistors.
  29. Antonino Schillaci IT; Antonio Grimaldi IT; Giuseppe Ferla IT, Edge termination of semiconductor devices for high voltages with resistive voltage divider.
  30. Hadizad Peyman ; Shen Zheng ; Salih Ali, Edge termination structure.
  31. Goetze Volkmar (Grafenau DEX) Miersch Ekkehard F. (Boeblingen DEX) Potz Guenther (Sindelfingen DEX), Electrically switchable permanent storage.
  32. Shim Hyun Woong,KRX ; Koo Bon Seong,KRX, Element isolation method for semiconductor devices including etching implanted region under said spacer to form a stepped trench structure.
  33. Hshieh Fwu-Iuan, Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area.
  34. Boiteux, Yves Pierre; Chen, Hui; Gregoratto, Ivano; Hsieh, Chang-Lin; Hung, Hoiman; Tang, Sum-Yee Betty, Etch process for dielectric materials comprising oxidized organo silane materials.
  35. Kim Jong Dae,KRX ; Kim Sang Ki,KRX ; Koo Jin Gun,KRX ; Nam Kee Soo,KRX, Fabrication method of lateral double diffused MOS transistors.
  36. Bulucea Constantin, Fabrication of complementary field-effect transistors each having multi-part channel.
  37. Cogan Adrian I. (San Jose CA), Fabrication of double diffused metal oxide semiconductor transistor.
  38. D'Anna Pablo Eugenio, Fabrication of lateral RF MOS devices with enhanced RF properties.
  39. Calafut, Daniel S., Field coupled power MOSFET bus architecture using trench technology.
  40. Kitagawa, Mitsuhiko; Aizawa, Yoshiaki, Field effect transistor and application device thereof.
  41. Brian Sze-Ki Mo ; Duc Chau ; Steven Sapp ; Izak Bencuya ; Dean Edward Probst, Field effect transistor and method of its manufacture.
  42. Tihanyi Jenoe,DEX, Field effect-controllable semiconductor component.
  43. Tihanyi Jeno,DEX ; Strack Helmut,DEX ; Geiger Heinrich,DEX, Field effect-controlled semiconductor component.
  44. Trujillo, Johann T.; Xie, Chenggang, Field emission device and method of operation.
  45. Paivinen John O. (Newtown Square PA) Eisenhower Walter D. (Audubon PA), Field inversion control for N-channel device integrated circuits.
  46. Jenoe Tihanyi DE, Field-effect transistor having a high packing density and method for fabricating it.
  47. Esquivel Agerico L. (Dallas TX) Mitchell Allan T. (Dallas TX) Tigelaar Howard L. (Dallas TX), Floating gate memory cell and device.
  48. Hall Donald M. (P.O. Box 1247 ; 19 Progress St. Kingston NY 12401-0119), Footed cart having normally disengaged wheels.
  49. Baliga Bantval J. (Clifton Park NY), Gate enhanced rectifier.
  50. Blanchard Richard A. (Los Altos CA), Grooved DMOS process with varying gate dielectric thickness.
  51. Inoue, Tomoki, High breakdown voltage semiconductor device.
  52. Norio Yasuhara JP; Kazutoshi Nakamura JP; Yusuke Kawaguchi JP, High breakdown voltage semiconductor device having trenched film connected to electrodes.
  53. Rajeevakumar Thekkemadathil V. (Scarsdale NY), High capacity DRAM trench capacitor and methods of fabricating same.
  54. Kocon Christopher B. ; Zeng Jun, High density MOS-gated power device and process for forming same.
  55. Hwang Wei (Armonk NY) Lu Nicky C. (Yorktown Heights NY), High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and.
  56. Tsang Dah W. (Bend OR) Mosier ; II John W. (Bend OR) Pike ; Jr. Douglas A. (Bend OR) Meyer Theodore O. (Bend OR), High density power device fabrication process.
  57. Hshieh Fwu-Iuan ; Floyd Brian H. ; Chang Mike F. ; Nim Danny ; Ng Daniel, High density trench DMOS transistor with trench bottom implant.
  58. Cogan, Adrian I.; Thornton, Neill R., High frequency JFET.
  59. Malhi Satwinder (Garland TX), High performance high voltage vertical transistor and method of fabrication.
  60. Eddie Huang GB, High voltage MOSFET with geometrical depletion layer enhancement.
  61. Neilson John M. S., High voltage mosfet structure.
  62. Milton J. Boden, Jr., High voltage mosgated device with trenches to reduce on-resistance.
  63. Deboy, Gerald; Tihanyi, Jenoe; Strack, Helmut; Gassel, Helmut; Stengl, Jens-Peer; Weber, Hans, High voltage resistant edge structure for semiconductor components.
  64. Coe David J. (Redhill GBX), High voltage semiconductor device.
  65. Neilson John M. S., High voltage semiconductor structure.
  66. Blanchard Richard A., High voltage termination with buried field-shaping region.
  67. Bencuya Izak (San Jose CA), High voltage transistor having edge termination utilizing trench technology.
  68. Okada David N. (Tempe AZ), High voltage transistor having reduced on-resistance.
  69. Kinzer, Daniel M.; Sridevan, Srikant, High voltage vertical conduction superjunction semiconductor device.
  70. Jenoe Tihanyi DE, High-voltage edge termination for planar structures.
  71. Deboy, Gerald; Ahlers, Dirk; Strack, Helmut; Rueb, Michael; Weber, Hans, High-voltage semiconductor component.
  72. Rumennik Vladimir ; Disney Donald R. ; Ajit Janardhanan S., High-voltage transistor with multi-layer conduction region.
  73. Banerjee,Sujit; Disney,Donald Ray, High-voltage vertical transistor with a multi-gradient drain doping profile.
  74. Disney, Donald Ray, High-voltage vertical transistor with a multi-layered extended drain structure.
  75. Pike ; Jr. Douglas A. (Bend OR) Tsang Dah W. (Bend OR) Katana James M. (Bend OR), IGBT process to produce platinum lifetime control.
  76. Tokura Norihito (Okazaki JPX) Okabe Naoto (Chita JPX) Kato Naohito (Kariya JPX), Insulated gate bipolar transistor with reverse conducting current.
  77. Majumdar Gourab (Tokyo JPX) Iwagami Touru (Tokyo JPX), Insulated gate semiconductor device.
  78. Temple Victor A. K. (Clifton Park NY), Insulated gate semiconductor device with extra short grid and method of fabrication.
  79. Minato Tadaharu,JPX, Insulated-gate bipolar semiconductor device.
  80. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance.
  81. Baliga Bantval J. (Clifton Park NY), Inversion-mode insulated-gate gallium arsenide field-effect transistors.
  82. Cardwell ; Jr. Walter T. (217 Bedford Forrest Ave. Anderson SC 29621), Junction field-effect transistor controlled by merged depletion regions.
  83. Johnson Joseph Herbert ; D'Anna Pablo Eugenio, Lateral RF MOS device having a combined source structure.
  84. D'Anna Pablo Eugenio, Lateral RF MOS device with improved breakdown voltage.
  85. D'Anna Pablo Eugenio, Lateral RF MOS device with improved drain structure.
  86. Colak Sel (Briarcliff Manor NY), Lateral double-diffused MOS transistor device.
  87. Tihanyi Jenoe,DEX, Lateral high-voltage transistor.
  88. Williams Richard K. ; Darwish Mohamed ; Grabowski Wayne ; Cornell Michael E., Low resistance power MOSFET or other device containing silicon-germanium layer.
  89. Thapar, Naresh, Low voltage power MOSFET device and process for its manufacture.
  90. Blanchard Richard A. (Los Altos Hills CA), MOS Power transistor with improved high-voltage capability.
  91. Jenoe Tihanyi DE, MOS field-effect transistor with auxiliary electrode.
  92. Han Min-Koo,KRX ; Min Byung-Hyuk,KRX, MOS transistor having an offset resistance derived from a multiple region gate electrode.
  93. Yoon Yong Sun,KRX ; Baek Kyu Ha,KRX ; Nam Kee Soo,KRX, MOS transistor of semiconductor device and method of manufacturing the same.
  94. Christopher B. Kocon, MOS-gated devices with alternating zones of conductivity.
  95. Kocon Christopher B., MOS-gated power device having extended trench and doping zone and process for forming same.
  96. Christopher B. Kocon ; Thomas E. Grebs ; Joseph L. Cumbo ; Rodney S. Ridley, MOS-gated power device having segmented trench and extended doping zone and process for forming same.
  97. Franz Hirler DE; Wolfgang Werner DE, MOS-transistor structure with a trench-gate-electrode and a limited specific turn-on resistance and method for producing an MOS-transistor structure.
  98. So Koon Chong ; Tsui Yan Man ; Hshieh Fwu-Iuan ; Lin True-Lon ; Nim Danny Chi, MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches.
  99. Johnsen Robert J. (Scottsdale AZ) Sanders Paul W. (Scottsdale AZ), MOSFET with substrate source contact.
  100. Daniel M. Kinzer, MOSgated device with trench structure and remote contact and process for its manufacture.
  101. Kinzer Daniel M. ; Sridevan Srikant, MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance.
  102. Erwin A. Hijzen NL; Henricus G. R. Maas NL; Cornelius E. Timmering NL, Manufacture of trench-gate semiconductor devices.
  103. Toru Takeda JP; Tetsujiro Tsunoda JP, Manufacturing method of semiconductor device.
  104. Kawaguchi Hiroshi,JPX, Manufacturing method of semiconductor integrated circuit.
  105. Kang Dae K. (Kyungki KRX), Metal oxide semiconductor field effect transistor and method of making the same.
  106. Kocon, Christopher B.; Elbanhawy, Alan, Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses.
  107. Meyerson Bernard Steele, Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers.
  108. Pfiester James R. (Austin TX), Method for fabricating MOS transistors having gates with different work functions.
  109. Han Min-Koo (Seoul KRX) Min Byung-Hyuk (Seoul KRX), Method for fabricating a MOS transistor having an offset resistance.
  110. Chen Chien-Hung,TWX ; Wu Chih-Ta,TWX ; Lin Ching-Shun,TWX ; Chen Juinn-Sheng,TWX, Method for fabricating a concave bottom oxide in a trench.
  111. D'Anna Pablo Eugenio, Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection.
  112. Richard A. Blanchard ; Jean-Michel Guillot IE, Method for fabricating a power semiconductor device having a floating island voltage sustaining layer.
  113. Hshieh Fwu-Iuan (Santa Clara CA) Chang Mike F. (Santa Clara CA) Yilmaz Hamza (Saratoga CA), Method for fabricating a short channel trenched DMOS transistor.
  114. Henninger,Ralf; Hirler,Franz; Krumrey,Joachim; Rieger,Walter; P철lzl,Martin; Hofer,Heimo, Method for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration.
  115. Bencuya Izak (San Jose CA), Method for fabricating high voltage transistor having trenched termination.
  116. D'Anna Pablo Eugenio, Method for fabricating lateral RF MOS devices with enhanced RF properties.
  117. Lin, Chi-Hui; Lin, Jeng-Ping; Lee, Pei-Ing; Lien, Jih-Chang, Method for fabricating split gate flash memory cell.
  118. Balasubramanian Narayanan,SGX ; Kong Ching Win,SGX ; Jang Chuck,SGX, Method for forming a low impurity diffusion polysilicon layer.
  119. Euen Wolfgang (Boeblingen DEX) Hagmann Dieter (Wildberg DEX) Wildau Hans-Jurgen (Berlin DEX), Method for forming a thin dielectric layer on a substrate.
  120. Herrick,Robert; Losee,Becky; Probst,Dean, Method for forming a trench MOSFET having self-aligned features.
  121. Lu Chin-Yuan (Hsinchu TWX) Tseng Horng-Huei (Hsin TWX), Method for forming a vertical transistor with a stacked capacitor DRAM cell.
  122. Uenishi Akio,JPX ; Minato Tadaharu,JPX, Method for forming high breakdown semiconductor device.
  123. Cooper Kent J. (Austin TX) Lin Jung-Hui (Austin TX) Roth Scott S. (Austin TX) Roman Bernard J. (Austin TX) Mazure Carlos A. (Austin TX) Nguyen Bich-Yen (Austin TX) Ray Wayne J. (Austin TX), Method for forming pitch independent contacts and a semiconductor device having the same.
  124. Chien-Lung Chu TW, Method for forming stepped contact hole for semiconductor devices.
  125. Blanchard,Richard A., Method for forming thick dielectric regions using etched trenches.
  126. Witek Keith E., Method for forming trench transistor structure.
  127. Witek Keith E., Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase.
  128. Blanchard Richard A. (Los Altos CA), Method for increasing the performance of trenched devices and the resulting structure.
  129. Blanchard Richard A. (Los Altos CA), Method for making planar vertical channel DMOS structures.
  130. Chen Ling (Sunnyvale CA) Sung Hung-Cheng (Kaohsinng TWX) Lo Chi-Shiung (Hsinchu TWX), Method for making self-aligned source/drain mask ROM memory cell using trench etched channel.
  131. Yilmaz Hamza (Saratoga CA) Hshieh Fwu-Iuan (San Jose CA), Method for making termination structure for power MOSFET.
  132. Yang Sheng-Hsing (Hsinchu TWX), Method for manufacturing a VDMOS transistor.
  133. Hisamoto Dai (Kokubunji JPX) Kaga Toru (Urawa JPX) Kimura Shinichiro (Hachioji JPX) Moniwa Masahiro (Hannou JPX) Tanaka Haruhiko (Kokubunji JPX) Hiraiwa Atsushi (Kodaira JPX) Takeda Eiji (Koganei JPX, Method for manufacturing a semiconductor device and a semiconductor memory device.
  134. Hshieh,Fwu Iuan; So,Koon Chong; Pratt,Brian D., Method for manufacturing a superjunction device with wide mesas.
  135. Lou Chine-Gie,TWX, Method for manufacturing stacked capacitor.
  136. Hui Chi-Hung (Cupertino CA) Voorde Paul V. (Mountain View CA) Moll John L. (Palo Alto CA), Method for producing recessed field oxide with improved sidewall characteristics.
  137. Chang Chuan C. (Berkeley Heights NJ) Cooper ; Jr. James A. (Warren NJ) Kahng Dawon (Bridgewater Township ; Somerset County NJ) Murarka Shyam P. (New Providence NJ), Method of fabricating MOS field effect transistors.
  138. Lu Chih-Yuan,TWX ; Sung Janmye,TWX, Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circ.
  139. Hou Chia-Hsin,TWX ; Lin Jyh-Kuang,TWX ; Jung Tz-Guei,TWX ; Ko Joe,TWX, Method of fabricating a mixed circuit capacitor.
  140. Kwan Sze-Hon (Sunnyvale CA) Bencuya Izak (San Jose CA), Method of fabricating a self-aligned contact trench DMOS transistor structure.
  141. Vinal Albert W. (Cary NC) Dennen Michael W. (Raleigh NC), Method of fabricating field effect transistor having polycrystalline silicon gate junction.
  142. Richard A. Blanchard, Method of fabricating high voltage power MOSFET having low on-resistance.
  143. Hebert Francois (Sunnyvale CA) Kwan Sze-Hon (Sunnyvale CA) Bencuya Izak (San Jose CA), Method of fabricating self-aligned contact trench DMOS transistors.
  144. Numazawa Sumito,JPX ; Nakazawa Yoshito,JPX ; Kobayashi Masayoshi,JPX ; Kudo Satoshi,JPX ; Imai Yasuo,JPX ; Kubo Sakae,JPX ; Shigematsu Takashi,JPX ; Ohnishi Akihiro,JPX ; Uesawa Kozo,JPX ; Oishi Kent, Method of fabricating semiconductor device.
  145. Wong Hon-Sum P. (Peekskill NY), Method of fabricating sidewall charge-coupled device with trench isolation.
  146. Lan Ellen ; Huang Jenn-Hwa ; Eisenbeiser Kurt ; Wang Yang, Method of fabricating vertical FET with sidewall gate electrode.
  147. Lai Yeong-Chih,TWX, Method of forming a dual damascene structure on a semiconductor wafer.
  148. Marchant, Bruce D., Method of forming a field effect transistor having a lateral depletion structure.
  149. Brask,Justin K.; Doyle,Brian S.; Kavalleros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Method of forming a metal oxide dielectric.
  150. Hshieh Fwu-Iuan ; So Koon Chong, Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance.
  151. Fwu-Iuan Hshieh ; Koon Chong So, Method of forming a trench DMOS having reduced threshold voltage.
  152. Michaelis Alexander, Method of forming a trench capacitor using a rutile dielectric material.
  153. Smayling Michael C. (Missouri City TX) Reynolds Jack (Dallas TX), Method of forming insulated gate field-effect transistors.
  154. Ueno Katsunori (Nagano JPX), Method of forming silicon carbide trench mosfet with a schottky electrode.
  155. Parekh Kunal R. ; Li Li, Method of forming trench isolation region for semiconductor device.
  156. Yedinak, Joseph A.; Reichl, Dwayne S.; Lange, Douglas J., Method of isolating the current sense on power devices while maintaining a continuous stripe cell.
  157. Yedinak,Joseph A.; Reichl,Dwayne S.; Lange,Douglas J., Method of isolating the current sense on power devices while maintaining a continuous stripe cell.
  158. Richardson William F. (Richardson TX) Malhi Satwinder S. (Garland TX), Method of making DRAM cell with trench capacitor.
  159. Miwa Hiroyuki (Kanagawa JPX), Method of making a MOS semiconductor device.
  160. Chang Mike F. (Cupertino CA) Hshieh Fwu-Iuan (San Jose CA) Kwan Sze-Hon (San Francisco CA) Owyang King (Atherton CA), Method of making a field effect trench transistor having lightly doped epitaxial region on the surface portion thereof.
  161. Kenney Donald M. (Shelburne VT), Method of making a high density V-MOS memory array.
  162. Rumennik Vladimir ; Disney Donald R. ; Ajit Janardhanan S., Method of making a high-voltage transistor with multiple lateral conduction layers.
  163. Mathew Leo ; Kamekona Keith G. ; Tran Huy Trong ; Venkatraman Prasad ; Pearse Jeffrey ; Nguyen Bich-Yen, Method of making a power switching trench MOSFET having aligned source regions.
  164. Acovic Alexandre (Yorktown Heights NY) Hsu Ching-Hsiang (Hsin Chu TWX) Wu Being S. (Yorktown Heights NY), Method of making a three dimensional trench EEPROM cell structure.
  165. Cogan Adrian I. (San Jose CA) Blanchard Richard A. (Los Altos CA), Method of making a vertical current flow field effect transistor.
  166. Iranmanesh Ali (Mountain View CA), Method of making an isolation slot for integrated circuit structure.
  167. Floyd Brian H. ; Hshieh Fwu-Iuan ; Chang Mike F., Method of making punch-through field effect transistor.
  168. Cogan Adrian I. (San Jose CA) Blanchard Richard A. (Los Altos CA), Method of making vertical current flow field effect transistor.
  169. Omura Yasuhisa (Kanagawa JPX) Kunii Yasuo (Kanagawa JPX) Izumi Katsutoshi (Kanagawa JPX), Method of manufacturing SOI semiconductor element.
  170. Anderson Dirk N. (Plano TX), Method of manufacturing a minimum scaled transistor.
  171. Hshieh,Fwu Iuan, Method of manufacturing a superjunction device with conventional terminations.
  172. Chang Chang V. J. M. (Eindhoven NLX) Rijpers Johannes C. N. (Eindhoven NLX), Method of manufacturing an optoelectronic semiconductor device.
  173. Mori Seiichi (Tokyo JPX), Method of manufacturing capacitor.
  174. Hieda Katsuhiko (Yokohama JPX), Method of manufacturing dynamic RAM.
  175. Ishikawa Hiraku,JPX, Method of manufacturing isolation trenches using silicon nitride liner.
  176. Chen Yen-Ming,TWX ; Liu Wei-Jen,TWX ; Lin Shih-Chi,TWX ; Liu Kuo-Chou,TWX, Method of manufacturing self-aligned T-shaped gate through dual damascene.
  177. Kubo Hirotoshi,JPX ; Kuwako Eiichiroh,JPX ; Kitagawa Masanao,JPX ; Onda Masahito,JPX ; Saitou Hiroaki,JPX ; Odajima Keita,JPX, Method of manufacturing semiconductor device.
  178. Yamaguchi,Masakazu; Saito,Wataru; Omura,Ichiro; Izumisawa,Masaru, Method of manufacturing semiconductor device.
  179. Fujishima Naoto,JPX, Method of manufacturing vertical trench misfet.
  180. Kim Manjin J. (Hartsdale NY), Method of producing VDMOS device of increased power density.
  181. Krautschneider Wolfgang,DEX ; Risch Lothar,DEX ; Hofmann Franz,DEX, Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells.
  182. Bashir Rashid, Method of producing high quality silicon surface for selective epitaxial growth of silicon.
  183. Baba Yoshiro (Yokohama JPX) Hiraki Shunichi (Chiba JPX) Osawa Akihiko (Machida JPX) Yanagiya Satoshi (Kawasaki JPX), Method of production of vertical MOS transistor.
  184. Paul Antony Jerred GB, Method of semiconductor device fabrication.
  185. Lim Chong Wee,MYX ; Siah Soh Yun,SGX ; Lim Eng Hua,SGX ; Lee Kong-Hean,SGX ; Low Chun Hui,MYX, Method to form shallow trench isolations with rounded corners and reduced trench oxide recess.
  186. Bantval Jayant Baliga, Methods of forming power semiconductor devices having tapered trench-based insulating regions therein.
  187. Lee Tea-Sun,KRX ; Song Sung-Kyu,KRX, Methods of forming semiconductor switching devices having trench-gate electrodes.
  188. Steven Paul Sapp, Monolithically integrated trench MOSFET and Schottky diode.
  189. Korman Charles S. (Schenectady NY) Baliga Bantval J. (Raleigh NC) Chang Hsueh-Rong (Scotia NY), Multicellular FET having a Schottky diode merged therewith.
  190. Williams Richard K., Multiple gated MOSFET for use in DC-DC converter.
  191. Williams Richard K. (Cupertino CA), Multiple gated MOSFET for use in DC-DC converter.
  192. Chang Robert Pang Heng (Warren NJ) Sinha Ashok Kumar (Murray Hill NJ), Native growth of semiconductor oxide layers.
  193. Rama Divakaruni ; Stephan Kudelka ; Helmut Tews ; Irene McStay ; Kil-Ho Lee ; Uwe Schroeder DE, Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation.
  194. Yamazaki Shunpei (Tokyo JPX) Takemura Yasuhiko (Kanagawa JPX), Non-volatile memory device having a floating gate.
  195. Fujii Tetsuo (Toyohashi JPX) Sakakibara Nobuyoshi (Hekinan JPX) Sakakibara Toshio (Nishio JPX) Iwasaki Hiroshi (Kawanishi JPX), Non-volatile semiconductor memory device.
  196. Chi Kao M. (Hsin-Chu TWX), PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof.
  197. Fujihira Tatsuhiko,JPX, Parallel-stripe type semiconductor device.
  198. Blanchard, Richard, Planar vertical channel DMOS structure.
  199. Wu Shye-Lin,TWX, Planarized deep-shallow trench isolation for CMOS/bipolar devices.
  200. Prall Kirk D. (Boise ID), Plug-based floating gate memory.
  201. Calafut, Daniel S., Power MOS device with improved gate charge performance.
  202. Daniel S. Calafut, Power MOS device with improved gate charge performance.
  203. Tihanyi Jenoe (Mnchen DEX), Power MOSFET.
  204. de Fresart Edouard D. ; Tam Pak ; Tsoi Hak-Yam, Power MOSFET device having low on-resistance and method.
  205. Izumisawa, Masaru; Kouzuki, Shigeo; Hodama, Shinichi, Power MOSFET semiconductor device and method of manufacturing the same.
  206. Izumisawa,Masaru; Kouzuki,Shigeo; Hodama,Shinichi, Power MOSFET semiconductor device and method of manufacturing the same.
  207. Wodarczyk Paul J. (Mountaintop PA) Jones Frederick P. (Mountaintop PA) Neilson John M. S. (Norristown PA) Yedinak Joseph A. (Wilkes-Barre PA), Power MOSFET transistor circuit with active clamp.
  208. Jones Frederick P. (Mountaintop PA) Yedinak Joseph A. (Wilkes-Barre PA) Neilson John M. S. (Norristown PA) Wrathall Robert S. (Durham NC) Mansmann Jeffrey G. (Raleigh NC) Jackoski Claire E. (Durham N, Power VDMOSFET with schottky on lightly doped drain of lateral driver FET.
  209. Yilmaz Hamza (Saratoga CA), Power metal-oxide-semiconductor field effect transistor.
  210. Chang Hsueh-Rong (Scotia NY) Baliga Bantval J. (Raleigh NC) Tong David W. (Scotia NY), Power rectifier with trenches.
  211. Kawaguchi Yusuke,JPX ; Nakamura Kazutoshi,JPX ; Nakagawa Akio,JPX, Power semiconductor device.
  212. Omura Ichiro (Yokohama JPX) Kitagawa Mitsuhiko (Tokyo JPX) Nakayama Kazuya (Sagamihara JPX) Yamaguchi Masakazu (Tokyo JPX), Power semiconductor device.
  213. Challa,Ashok; Elbanhawy,Alan; Sapp,Steven P.; Wilson,Peter H.; Sani,Babak S.; Kocon,Christopher B., Power semiconductor devices and methods of manufacture.
  214. Baliga Bantval Jayant, Power semiconductor devices having improved high frequency switching and breakdown characteristics.
  215. Bantval Jayant Baliga, Power semiconductor devices having trench-based gate electrodes and field plates.
  216. Baliga Bantval Jayant, Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same.
  217. Omura, Ichiro; Saito, Wataru; Ogura, Tsuneo; Ohashi, Hiromichi; Saito, Yoshihiko; Tokano, Kenichi, Power semiconductor switching element provided with buried electrode.
  218. So Koon Chong ; Hshieh Fwu-Iuan, Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask.
  219. Gossmann Hans-Joachim Ludwig ; Rafferty Conor Stefan, Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby.
  220. Eaglesham David James ; Gossmann Hans-Joachim Ludwig ; Poate John Milo ; Stolk Peter Adriaan, Process for controlling dopant diffusion in a semiconductor layer and semiconductor layer formed thereby.
  221. Himelick James M. (Kokomo IN), Process for manufacture of a vertical DMOS transistor.
  222. Nance Paul,DEX ; Werner Wolfgang,DEX, Process for producing an epitaxial layer with laterally varying doping.
  223. Herman,Thomas, Process for resurf diffusion for high voltage MOSFET.
  224. Buiguez Francois (Saint Egieve FRX) Hartmann Jol (Claix FRX), Process for the autopositioning of a local field oxide with respect to an insulating trench.
  225. Williams Richard K. ; Grabowski Wayne B., Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses.
  226. Huang Tzuen-Hsi,TWX ; Lee Chwan-Ying,TWX, Process to manufacture a vertical gate-enhanced bipolar transistor.
  227. Floyd Brian H. (Sunnyvale CA) Hshieh Fwu-Iuan (Saratoga CA) Chang Mike F. (Cupertino CA), Punch-through field effect transistor.
  228. Johnson Joseph Herbert ; D'Anna Pablo Eugenio, Quasi-mesh gate structure for lateral RF MOS devices.
  229. D'Anna Pablo Eugenio, RF power MOSFET device with extended linear region of transconductance characteristic at low drain current.
  230. Mehrotra Manoj (Raleigh NC) Baliga Bantval J. (Raleigh NC), Schottky barrier rectifier with MOS trench.
  231. Tan Allen, Schottky diode with dielectric trench.
  232. Hine Shiro (Itami JPX), Selective epitaxial growth method.
  233. Beasom James D. (Melbourne Village FL), Self-aligned channel stop for trench-isolated island.
  234. Kwan Sze-Hon ; Bencuya Izak ; Sapp Steven P., Self-aligned method of fabricating terrace gate DMOS transistor.
  235. Tsang Dah Wen ; Mosier ; II John W. ; Pike ; Jr. Douglas A. ; Meyer Theodore O., Self-aligned power MOSFET device with recessed gate and source.
  236. Hebert Francois ; Ng Szehim, Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability.
  237. Teshigahara Akihiko,JPX ; Asai Akiyoshi,JPX ; Onoda Kunihiro,JPX ; Itou Hiroyasu,JPX ; Abe Ryuichirou,JPX ; Sakakibara Toshio,JPX, Semiconductor apparatus having high withstand voltage.
  238. Hshieh Fwu-Iuan, Semiconductor cell array with high packing density.
  239. Wolfgang Werner DE, Semiconductor component.
  240. Pfirsch Frank,DEX, Semiconductor component having a small forward voltage and high blocking ability.
  241. Deboy Gerald,DEX ; Stengl Jens-Peer,DEX ; Tihanyi Jenoe,DEX ; Graf Heimo,ATX, Semiconductor component which can be controlled by a field effect.
  242. Henninger, Ralf; Hirler, Franz; Krumrey, Joachim; Zundel, Markus; Rieger, Walter; Pölzl, Martin, Semiconductor component with an increased breakdown voltage in the edge area.
  243. Werner Wolfgang,DEX ; Tihanyi Jenoe,DEX, Semiconductor component with metal-semiconductor junction with low reverse current.
  244. Iwamoto, Susumu; Fujihira, Tatsuhiko; Ueno, Katsunori; Onishi, Yasuhiko; Sato, Takahiro; Nagaoka, Tatsuji, Semiconductor device.
  245. Kouzuki, Shigeo; Okumura, Hideki; Kobayashi, Hitoshi; Aida, Satoshi; Izumisawa, Masaru; Osawa, Akihiko, Semiconductor device.
  246. Nishizawa Jun-ichi (Sendai JPX), Semiconductor device.
  247. Ogura Tsuneo,JPX ; Yamaguchi Masakazu,JPX, Semiconductor device.
  248. Omura Ichiro,CHX ; Inoue Tomoki,JPX ; Ohashi Hiromichi,JPX, Semiconductor device.
  249. Yukimoto Yoshinori (Itami JPX), Semiconductor device.
  250. Stuart E. Greer, Semiconductor device and a process for forming the semiconductor device.
  251. Nakamura Hideki,JPX ; Minato Tadaharu,JPX, Semiconductor device and manufacturing method thereof.
  252. Shen Zheng ; Robb Francine Y. ; Robb Stephen P., Semiconductor device and method of manufacture.
  253. Masana Harada JP, Semiconductor device and method of manufacturing thereof.
  254. Mori Mutsuhiro (Mito JPX) Yasuda Yasumichi (Hitachi JPX) Hosoya Hiromi (Hitachi JPX), Semiconductor device and power converter using same.
  255. Onishi, Yasuhiko; Fujihira, Tatsuhiko; Iwamoto, Susumu; Sato, Takahiro, Semiconductor device and the method of manufacturing the same.
  256. Yamamoto Tsuyoshi,JPX ; Naito Masami,JPX ; Fukazawa Takeshi,JPX, Semiconductor device having a gate electrode in a grove and a diffused region under the grove.
  257. Fujihira Tatsuhiko,JPX, Semiconductor device having a plurality of parallel drift regions.
  258. Godefridus A. M. Hurkx NL; Rob Van Dalen NL, Semiconductor device having a plurality of resistive paths.
  259. Goodyear Andrew L. (Red Hill GB2) Hutchings Keith M. (Groombridge GB2), Semiconductor device having a vertical insulated gate field effect device and a breakdown region remote from the gate.
  260. Suzuki,Takashi; Uesugi,Tsutomu; Tokura,Norihito, Semiconductor device having a vertical type semiconductor element.
  261. Disney Donald R. (Kokomo IN) Sozansky Wayne A. (Greentown IN) Himelick James M. (Kokomo IN), Semiconductor device having field limiting ring and a process therefor.
  262. Kawashima Shoichiro (Kawasaki JPX), Semiconductor device having transistor pair.
  263. Nishihara Hidenori (Hyogo JPX), Semiconductor device having trench structure.
  264. Okumura,Hideki; Kobayashi,Hitoshi; Tsuchitani,Masanobu; Osawa,Akihiko; Saito,Wataru; Yamaguchi,Masakazu; Omura,Ichiro, Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type.
  265. Kohyama Yusuke,JPX, Semiconductor device including an improved terminal structure.
  266. Fujihira, Tatsuhiko, Semiconductor device with alternating conductivity type layer and method of manufacturing the same.
  267. Miyasaka Yasushi,JPX ; Fujihira Tatsuhiko,JPX ; Ohnishi Yasuhiko,JPX ; Ueno Katsunori,JPX ; Iwamoto Susumu,JPX, Semiconductor device with alternating conductivity type layer and method of manufacturing the same.
  268. Miyasaka, Yasushi; Fujihira, Tatsuhiko, Semiconductor device with alternating conductivity type layer and method of manufacturing the same.
  269. Shindou, Youichi; Miyasaka, Yasushi; Fujihira, Tatsuhiko; Takei, Manabu, Semiconductor device with alternating conductivity type layer and method of manufacturing the same.
  270. Ludikhuize Adrianus W. (Eindhoven NLX), Semiconductor device with an MOST provided with an extended drain region for high voltages.
  271. Matsushita Takeshi (Sagamihara JA) Hayashi Hisao (Atsugi JA), Semiconductor device with high voltage breakdown resistance.
  272. Yamaguchi, Masakazu; Saito, Wataru; Omura, Ichiro; Izumisawa, Masaru, Semiconductor device with super junction region.
  273. Gajda, Mark A.; in 't Zandt, Michael A. A.; Hijzen, Erwin A., Semiconductor devices and their manufacture.
  274. Cardwell ; Jr. Walter T. (217 Bedford Forrest Ave. Anderson SC 29621), Semiconductor devices controlled by depletion regions.
  275. Temple Victor A. K. (Clifton Park NY), Semiconductor devices exhibiting minimum on-resistance.
  276. Takahashi Hideki (Fukuoka JPX), Semiconductor diode with reduced recovery current.
  277. Tsuchitani Masanobu,JPX ; Suzuki Keita,JPX ; Osawa Akihiko,JPX ; Baba Yoshiro,JPX, Semiconductor gate trench with covered open ends.
  278. Kinzer Daniel M. (Riverside CA), Semiconductor high-power mosfet device.
  279. Chen Xingbi (Sichuan CNX), Semiconductor power devices with alternating conductivity type high-voltage breakdown regions.
  280. Nitta Tetsuya,JPX ; Minato Tadaharu,JPX ; Uenisi Akio,JPX, Semiconductor resurf devices formed by oblique trench implantation.
  281. Groenig Paul J., Semiconductor structure with field-limiting rings and method for making.
  282. Kocon, Christopher Boguslaw, Semiconductor structure with improved smaller forward voltage loss and higher blocking capability.
  283. Huang Qin, Semiconductor structures with trench contacts.
  284. Qin Huang, Semiconductor structures with trench contacts.
  285. Wollesen Donald L. ; Fatemi Homi, Short channel self-aligned VMOS field effect transistor.
  286. Singh Ranbir ; Palmour John W., Silicon carbide metal-insulator semiconductor field effect transistor.
  287. Baliga Bantval J. (Raleigh NC), Silicon carbide power MOSFET with floating field ring and floating field plate.
  288. Baliga Bantval Jayant, Silicon carbide power devices having trench-based silicon carbide charge coupling regions therein.
  289. Miyajima Takeshi,JPX ; Tokura Norihito,JPX ; Hara Kazukuni,JPX ; Fuma Hiroo,JPX, Silicon carbide semiconductor device.
  290. Yamamoto Tsuyoshi,JPX ; Kumar Rajesh,JPX ; Hara Kunihiko,JPX ; Takeuchi Yuichi,JPX ; Hara Kazukuni,JPX ; Naito Masami,JPX, Silicon carbide semiconductor device and manufacturing method thereof.
  291. Roman J. Hamerski, Single step etched moat.
  292. D'Anna Pablo Eugenio ; Johnson Joseph Herbert, Source connection structure for lateral RF MOS devices.
  293. Corsi Marco ; Milam Stephen W. ; Cooley Gregory M., Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies.
  294. Zommer Nathan (Los Altos CA), Stable high voltage semiconductor device structure.
  295. Kenney Donald McAlpine, Stacked devices.
  296. Muraoka Kimihiro (Kanagawa JPX) Shimizu Naohiro (Kanagawa JPX) Tamamushi Takashige (Tokyo JPX), Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor dev.
  297. Herrick, Robert; Losee, Becky; Probst, Dean, Structure and method for forming a trench MOSFET having self-aligned features.
  298. So Koon Chong, Structure to provide effective channel-stop in termination areas for trenched power transistors.
  299. Bhalla, Anup; Pitzer, Dorman; Korec, Jacek; Shi, Xiaorong; Lui, Sik, Structures of and methods of fabricating trench-gated MIS devices.
  300. Onishi, Yasuhiko; Fujihira, Tatsuhiko; Ueno, Katsunori; Iwamoto, Susumu; Sato, Takahiro; Nagaoka, Tatsuji, Super-junction semiconductor device.
  301. Onishi, Yasuhiko; Fujihira, Tatsuhiko; Ueno, Katsunori; Iwamoto, Susumu; Sato, Takahiro; Nagaoka, Tatsuji, Super-junction semiconductor device.
  302. Sato, Takahiro; Ueno, Katsunori; Fujihira, Tatsuhiko; Kunihara, Kenji; Onishi, Yasuhiko; Iwamoto, Susumu, Super-junction semiconductor device.
  303. Gaul Stephen Joseph ; Delgado Jose Avelino, Surface mount die by handle replacement.
  304. Gerald Deboy DE; Franz Hirler DE; Martin Marz DE; Hans Weber DE, Switch mode power supply with reduced switching losses.
  305. Qu, Zhijun, Termination structure for superjunction device.
  306. Beilstein ; Jr. Kenneth Edward (Essex Junction VT) Bertin Claude Louis (So. Burlington VT) Cronin John Edward (Milton VT) White Francis Roger (Essex Junction VT), Three-dimensional SRAM trench structure and fabrication method therefor.
  307. Malhi Satwinder, Top-drain trench based resurf DMOS transistor structure.
  308. Malhi Satwinder (Garland TX), Top-drain trench based resurf DMOS transistor structure.
  309. Chang-Ki Jeon KR; Young-Soo Jang KR, Trench DMOS device having a high breakdown resistance.
  310. Choi Mun-Heui,KRX ; Jeong Dong-Soo,KRX, Trench DMOS device having an amorphous silicon and polysilicon gate.
  311. Bulucea Constantin (Sunnyvale CA) Rossen Rebecca (Palo Alto CA), Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry.
  312. Boden ; Jr. Milton J., Trench MOS device and process for radhard device.
  313. Beasom James Douglas, Trench MOS gate device.
  314. James Douglas Beasom, Trench MOS gate device.
  315. Hirler, Franz; Kotek, Manfred; Larik, Joost; Pfirsch, Frank, Trench MOS transistor.
  316. Blanchard Richard A. (Los Altos CA), Trench MOS-gated device with a minimum number of masks.
  317. Hshieh, Fwu-Iuan; So, Koon Chong; Amato, John E.; Tsui, Yan Man, Trench MOSFET device with improved on-resistance.
  318. Darwish Mohamed N., Trench MOSFET having improved breakdown and on-resistance characteristics.
  319. Fwu-Iuan Hshieh ; Koon Chong So, Trench MOSFET with double-diffused body profile.
  320. Hao, Jifa; Grebs, Thomas; Ridley, Rodney S.; Skurkey, Louise; Gasser, Chris, Trench MOSFET with low gate charge.
  321. Darwish Mohamed N. ; Williams Richard K., Trench MOSFET with multi-resistivity drain to provide low on-resistance.
  322. Fwu-Iuan Hshieh ; Koon Chong So ; Yan Man Tsui, Trench MOSFET with structure having low gate charge.
  323. Huang Qin, Trench contact process.
  324. Hshieh Fwu-Iuan ; Chang Mike F., Trench field effect transistor with reduced punch-through susceptibility and low R.sub.DSon.
  325. Baliga B. Jayant (Raleigh NC), Trench gate lateral MOSFET.
  326. Iwamatsu Seiichi (Nagano JPX), Trench gate metal oxide semiconductor field effect transistor.
  327. Chang Hsueh-Rong (Scotia NY), Trench gate structure with thick bottom oxide.
  328. Manning Monte (Kuna ID), Trench isolation using gated sidewalls.
  329. Cogan Adrian I. (San Jose CA) Thornton Neill R. (Alameda CA), Trench power MOSFET device.
  330. Williams, Richard K.; Cornell, Michael E.; Chan, Wai Tien, Trench power MOSFET with planarized gate bus.
  331. Henninger, Ralf; Hirler, Franz; Kotek, Manfred; Larik, Joost; Zundel, Markus, Trench power semiconductor.
  332. Witek Keith E., Trench random access memory cell and method of formation.
  333. Fulton Inge G. (Washingtonville NY) Makris James S. (Wappingers Falls NY) Nastasi Victor R. (Hopewell Junction NY) Scaduto Anthony F. (Newburgh NY) Shartel Anne C. (Pleasant Valley NY), Trench sidewall isolation by polysilicon oxidation.
  334. Challa, Ashok, Trench structure for semiconductor devices.
  335. Mo Brian S., Trench structure substantially filled with high-conductivity material.
  336. Mo Brian Sze-Ki, Trench transistor with a self-aligned source.
  337. Williams Richard K. ; Grabowski Wayne ; Darwish Mohamed ; Korec Jacek, Trench-gated MOSFET with bidirectional voltage clamping.
  338. Liu Yowjuang W. ; Wollesen Donald L., Trench-gated vertical combination JFET and MOSFET devices.
  339. Hshieh Fwu-Iuan (Saratoga CA) Chang Mike F. (Cupertino CA) Ho Yueh-Se (Sunnyvale CA) Owyang King (Atherton CA), Trenched DMOS transistor fabrication having thick termination region oxide.
  340. Hshieh Fwu-Iuan (Saratoga CA) Chang Mike F. (Cupertino CA) Ho Yueh-Se (Sunnyvale CA) Owyang King (Atherton CA), Trenched DMOS transistor having thick field oxide in termination region.
  341. Hshieh Fwu-Iuan (Saratoga CA) Chang Mike F. (Cupertino CA) Ching Lih-Ying (Cupertino CA) Ng Sze H. (Sunnyvale CA) Cook William (Fremont CA), Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness.
  342. Hshieh Fwu-Iuan ; Ching Lih-Ying ; Tran Hoang ; Chang Mike F., Trenched DMOS transistor with lightly doped tub.
  343. Erwin A. Hijzen NL; Raymond J. E. Hueting NL, Trenched Schottky rectifiers.
  344. Floyd Brian H. ; Pitzer Dorman C. ; Hshieh Fwu-Iuan ; Chang Mike F., Trenched field effect transistor with PN depletion barrier.
  345. Uenishi Akio,JPX ; Minato Tadaharu,JPX, Trenched high breakdown voltage semiconductor device.
  346. Zeng, Jun, Ultra dense trench-gated power-device with the reduced drain-source feedback capacitance and Miller charge.
  347. Yang Sheng-Hsing (Hsinchu TWX), VDMOS transistor and manufacturing method therefor.
  348. Baliga, Bantval Jayant, Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes.
  349. Cogan Adrian I. (San Jose CA) Blanchard Richard A. (Los Altos CA), Vertical current flow field effect transistor with thick insulator over non-channel areas.
  350. Baliga Bantval J. (Schenectady NY) Chow Tat-Sing P. (Schenectady NY) Chang Hsueh-Rong (Scotia NY), Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased s.
  351. Chang Hsueh-Rong (Scotia NY) Baliga Bantval J. (Schenectady NY) Chow Tat-Sing P. (Schenectady NY), Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method.
  352. Iwamoto, Susumu; Onishi, Yasuhiko; Sato, Takahiro; Nagaoka, Tatsuji, Vertical field effect transistor.
  353. Baliga Bantval J. (Raleigh NC), Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance.
  354. Kakumoto Munenari (Kawasaki JPX), Vertical insulated gate transistor and method of manufacture.
  355. Mori Kiyoshi (Stafford TX), Vertical memory cell array and method of fabrication.
  356. Williams Richard K., Vertical power MOSFET having reduced sensitivity to variations in thickness of epitaxial layer.
  357. Takahashi Nobumitsu (Tokyo JPX) Takahashi Mitsuasa (Tokyo JPX) Kubota Hitoshi (Tokyo JPX), Vertical power MOSFET structure having reduced cell area.
  358. Baliga, Bantval Jayant, Vertical power devices having trench-based electrodes therein.
  359. Fujishima Naoto,JPX, Vertical trench misfet and method of manufacturing the same.
  360. Yamauchi,Shoichi; Yamaguchi,Hitoshi; Suzuki,Takashi; Nakashima,Kyoko, Vertical type semiconductor device.
  361. Tokano,Keinichi; Saito,Yoshihiko; Kouzuki,Shigeo; Usui,Yasunori; Izumisawa,Masaru; Kawano,Takahiro, Vertical type semiconductor device and method of manufacturing the same.
  362. Sugawara Yoshitaka (Hitachi JPX), Voltage-driven type semiconductor device.

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  1. Le Tiec, Yannick; Andrieu, Francois, Method for making a semiconductor structure with a buried ground plane.
  2. West, Peter; Kosier, Steven; Kamimura, Tatsuya; Rankila, Don, Termination trench structures for high-voltage split-gate MOS devices.
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