IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0905556
(2013-05-30)
|
등록번호 |
US-8790989
(2014-07-29)
|
발명자
/ 주소 |
- Hsu, Louis L.
- Ouyang, Xu
- Yang, Chih-Chao
|
출원인 / 주소 |
- International Business Machines Corporation
|
대리인 / 주소 |
Scully, Scott, Murphy & Presser, P.C.
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인용정보 |
피인용 횟수 :
0 인용 특허 :
30 |
초록
▼
A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capaci
A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
대표청구항
▼
1. A method of manufacturing a semiconductor structure, said method comprising: forming at least one switching device on a semiconductor substrate by forming, for each of said at least one switching device, a first p-type field effect transistor and a second p-type field effect transistor that are c
1. A method of manufacturing a semiconductor structure, said method comprising: forming at least one switching device on a semiconductor substrate by forming, for each of said at least one switching device, a first p-type field effect transistor and a second p-type field effect transistor that are connected in a parallel connection between a power supply node and one node of a capacitor module;forming at least one capacitor-side via structure contacting one node of said at least one switching device; andforming at least two capacitors, said at least two capacitors comprising at least three conductive plates and at least one node dielectric on said semiconductor substrate, wherein said at least three conductive plates vertically overlie or underlie one another and are separated from one another by said at least one node dielectric, and a laterally protruding portion of one of said at least three conductive plates contacts said at least one capacitor-side via structure, wherein said at least three conductive plates and at least one node dielectric are components of said capacitor module. 2. The method of claim 1, further comprising: forming at least one power-supply-side via structure contacting another node of said at least one switching device; andforming a power-supply-side plate contacting said at least one power-supply-side via structure. 3. The method of claim 1, further comprising: forming a first conductive plate over said semiconductor substrate;forming a first node dielectric on an upper surface of said first conductive plate; andforming a second conductive plate on an upper surface of said first node dielectric. 4. The method of claim 1, further comprising: forming a second node dielectric on an upper surface of said second conductive plate; andforming a third conductive plate on an upper surface of said second node dielectric, wherein said at least three conductive plates includes said first, second, and third conductive plates and said at least one node dielectric includes said first and second node dielectrics. 5. The method of claim 4, wherein said first and second node dielectrics comprise a dielectric metal oxide material having a dielectric constant greater than 8.0, and said at least three conductive plates and at least one node dielectric constitute at least two capacitors wherein one of said at least three conductive plates is a common node of said at least two capacitors. 6. The method of claim 5, wherein said first p-type field effect transistor and said second p-type field effect transistor constitute a field effect transistor and a sensor unit configured to detect a leakage current through said at least two capacitors, and said at least two capacitors is formed at a location overlying said at least one switching device. 7. The method of claim 1, further comprising forming an array of capacitor modules, wherein said capacitor module is a unit module of said array of capacitor modules and comprises one of said at least one capacitor-side via structure and one of said at least one switching device. 8. The method of claim 7, wherein each capacitor among said at least two capacitors includes a first electrode, a second electrode, and a dielectric material located between said first electrode and said second electrode. 9. The method of claim 7, wherein each of said at least one switching device is configured to electrically disconnect said capacitor module from said power supply node when a leakage current detected by a sensor unit exceeds a predetermined level. 10. The method of claim 9, wherein said sensor unit is configured to provide a voltage to a gate of said field effect transistor, wherein said voltage is determined by said leakage current. 11. A method of manufacturing a semiconductor structure, said method comprising: forming at least one switching device on a semiconductor substrate, wherein each of said at least one switching device comprises a sensor unit, and is configured to electrically disconnect a capacitor module from a power supply node when a leakage current detected by said sensor unit exceeds a predetermined level;forming at least one capacitor-side via structure contacting one node of said at least one switching device; andforming at least two capacitors, said at least two capacitors comprising at least three conductive plates and at least one node dielectric on said semiconductor substrate, wherein said at least three conductive plates vertically overlie or underlie one another and are separated from one another by said at least one node dielectric, and a laterally protruding portion of one of said at least three conductive plates contacts said at least one capacitor-side via structure, wherein said at least three conductive plates and at least one node dielectric are components of said capacitor module, wherein, within each of said at least one switching device, said sensor unit comprises a first p-type field effect transistor, and a second p-type field effect transistor and said p type field effect transistors are connected in a parallel connection between said power supply node and one node of a capacitor within said capacitor module. 12. The method of claim 11, wherein a drain of said second p-type field effect transistor is connected directly to said power supply node, and a source of said second p-type field effect transistor is connected directly to said node of said capacitor. 13. The method of claim 11, wherein said sensor unit further comprises an even number of inverters in a series connection located between another node of said capacitor and a gate of said second p-type field effect transistor. 14. The method of claim 11, further comprising forming a pulse generator, wherein said pulse generator is configured to provide a signal pulse of a finite duration to a gate of said first p-type field effect transistor. 15. The method of claim 14, wherein said sensor unit further comprises a resistor configured to raise a temperature of said capacitor during a duration of said signal pulse. 16. The method of claim 1, wherein said at least one node dielectric is formed by: forming a first node dielectric directly on an upper surface of a first conductive plate among said at least three conductive plates;forming a second conductive plate among said at least three conductive plates on said first node dielectric;forming a second node dielectric directly on an upper surface of said second conductive plate among said at least three conductive plates; andforming a third conductive plate among said at least three conductive plates on said second node dielectric. 17. The method of claim 1, wherein one of said at least one switching device configured to electrically disconnect said capacitor module from a power supply node. 18. The method of claim 17, further comprising connecting one end of one of said at least one switching device to said power supply node and another end of said one of said at least one switching device to said capacitor module. 19. The method of claim 1, further comprising forming an array of vertically stacked capacitor modules, wherein each of said vertically stacked capacitor modules comprises one of said at least one switching device, one of said at least one capacitor-side via structure, and one of said at least one capacitor.
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