초록 ▼

A method for transmitting data between two storage virtualization controllers (SVCs) is disclosed in the present invention. The two SVCs comprising a first SVC and a second SVC, in which the first SVC comprises a first bus interface and a first memory, the second SVC comprises a second bus interface

A method for transmitting data between two storage virtualization controllers (SVCs) is disclosed in the present invention. The two SVCs comprising a first SVC and a second SVC, in which the first SVC comprises a first bus interface and a first memory, the second SVC comprises a second bus interface and a second memory, and an inter-controller communication channel (ICC) is established between the first bus interface and the second bus interface, the method comprising the steps of: transmitting, by the second SVC, a message via the ICC through the second bus interface to the first SVC, in which the message comprises a destination address of a block of the second memory, and the block is accessible; reading, by the first SVC, data in the first memory to be transmitted when the first SVC receives the message; transmitting, by the first SVC, the data to be transmitted and the destination address to the second SVC via the ICC through the first bus interface; and storing, by the second SVC, the transmitted data into the second memory according the destination address.

대표청구항 ▼

1. A method for transmitting data between two storage virtualization controllers (SVCs), the two SVCs comprising a first SVC and a second SVC, in which the first SVC comprises a first bus interface and a first memory, the second SVC comprises a second bus interface and a second memory, and an inter-

1. A method for transmitting data between two storage virtualization controllers (SVCs), the two SVCs comprising a first SVC and a second SVC, in which the first SVC comprises a first bus interface and a first memory, the second SVC comprises a second bus interface and a second memory, and an inter-controller communication channel (ICC) is established between the first bus interface and the second bus interface, the method comprising the steps of: establishing, by the second SVC, a data transmission table in the second memory;transmitting, by the second SVC a first message to the first SVC, in which the first message comprises a block size of the data transmission table in the second memory;recording a block in which data have been read by the second SVC;transmitting, by the second SVC, a second message via the ICC through the second bus interface to the first SVC, in which the second message comprises a destination address of the recorded block of the second memory, and the recorded block is accessible;reading, by the first SVC, data in the first memory to be transmitted when the first SVC receives the second message;transmitting, by the first SVC, the data to be transmitted and the destination address to the second SVC via the ICC through the first bus interface; andstoring, by the second SVC, the transmitted data into the second memory according the destination address. 2. The method according to claim 1, wherein the first SVC reads the data in the first memory to be transmitted according to a source address and a byte count of the data to be transmitted. 3. The method according to claim 1, wherein each of the SVCs comprises: a central processing circuit for performing an I/O operation in response to an I/O request from a host entity and for coupling to the other SVC via the bus interface;at least one I/O device interconnect controller coupled to the central processing circuit;at least one host-side port provided in the at least one I/O device interconnect controller for coupling to the host entity;at least one device-side port provided in the at least one I/O device interconnect controller for coupling to at least one physical storage device; anda memory coupled to the central processing circuit for buffering data transmitted between the host entity and the at least one physical storage device via the central processing circuit. 4. The method according to claim 3, wherein the central processing circuit comprises: a central processing unit (CPU); anda CPU chipset which is an interface between the CPU and other electronic components, the CPU chipset comprising: the bus interface for coupling to the other SVC;an internal main bus which is used as a communication connection among said other electronic components in the CPU chipset for communicating data signals and control signals; anda CPU interface coupled to the CPU and the internal main bus for communicating between the CPU and the other electronic components;a memory controller coupled to the memory and the internal main bus, in which when the memory controller receives the data transmitted from the internal main bus, the memory controller stores the data into the memory, and the data in the memory is transmitted to the internal main bus via the memory controller; anda third bus interface coupled to the at least one I/O device interconnect controller and the internal main bus for being an interface therebetween. 5. The method according to claim 4, wherein the CPU chipset further comprises a register belonging to the bus interface, and a third message associated with the data to be transmitted to the other SVC is written into a storage space of the register by the CPU. 6. The method according to claim 5, wherein the register is provided in the bus interface. 7. The method according to claim 1, wherein the first bus interface and the second bus interface are PCI-Express bus interfaces. 8. The method according to claim 1, wherein the data to be transmitted relate to data regarding control data. 9. The method according to claim 1, further comprising the step of: transmitting, by the second SVC, the second message to the first SVC, when one of blocks of the second memory of the second SVC is released, in which the second message comprises the destination address of the block. 10. The method according to claim 1, wherein the first and the second messages are a vendor-defined message or ignore message, both of which are defined by a PCI-Express. 11. A method for transmitting data between two storage virtualization controllers (SVCs), the SVCs comprises a first SVC and a second SVC, in which the first SVC comprises a first bus interface and a first memory, and the second SVC comprises a second bus interface and a second memory, and an inter-controller communication channel (ICC) is established between the first bus interface and the second bus interface, the method comprising the steps of: establishing, by the second SVC, a data transmission table in the second memory;transmitting, by the second SVC, a first message to the first SVC, in which the first message comprises a block size of the data transmission table in the second memory;recording a number of block in which data have been read by the second SVC, as a number of credit;transmitting, by the second SVC, the number of credit to the first SVC;reading, by the first SVC, the data to be transmitted according to the number of credit, and transmitting the data to be transmitted, to the second SVC, when the first SVC receives the number of credit from the second SVC; andstoring, by the second SVC, the transmitted data from the first SVC, into the data transmission table in the second memory of the second SVC, when the second SVC receives the transmitted data. 12. The method according to claim 11, wherein the first SVC reads the data in the first memory to be transmitted according to a source address and a byte count of the data to be transmitted. 13. The method according to claim 11, wherein each of the SVCs comprises: a central processing circuit for performing an I/O operation in response to an I/O request from a host entity and for coupling to the other SVC via the bus interface;at least one I/O device interconnect controller coupled to the central processing circuit;at least one host-side port provided in the at least one I/O device interconnect controller for coupling to the host entity;at least one device-side port provided in the at least one I/O device interconnect controller for coupling to at least one physical storage device; anda memory coupled to the central processing circuit for buffering data transmitted between the host entity and the at least one physical storage device via the central processing circuit. 14. The method according to claim 13, wherein the central processing circuit comprises: a central processing unit (CPU); anda CPU chipset which is an interface between the CPU and other electronic components, the CPU chipset comprising: the bus interface for coupling to the other SVC;an internal main bus which is used as a communication connection among said other electronic components in the CPU chipset for communicating data signals and control signals; anda CPU interface coupled to the CPU and the internal main bus for communicating between the CPU and the other electronic components;a memory controller coupled to the memory and the internal main bus, in which when the memory controller receives the data transmitted from the internal main bus, the memory controller stores the data into the memory, and the data in the memory is transmitted to the internal main bus via the memory controller; andan interface coupled to the at least one I/O device interconnect controller and the internal main bus for being an interface therebetween. 15. The method according to claim 14, wherein the CPU chipset further comprises a register belonging to the bus interface, and a second message associated with the data to be transmitted to the other SVC is written into a storage space of the register by the CPU. 16. The method according to claim 15, wherein the register is provided in the bus interface. 17. The method according to claim 11, wherein the first bus interface and the second bus interface are PCI-Express bus interface. 18. The method according to claim 11, wherein the data to be transmitted relate to data regarding control data. 19. The method according to claim 11, wherein the first message is a vendor-defined or ignore message, both of which are defined by a PCI-Express. 20. The method according to claim 11, wherein data of the data transmission table comprises a base address, a data length and the block size. 21. The method according to claim 1, further comprising steps of: reading, by the first SVC, data in the first memory to be transmitted and transmitting the data into the data transmission table in the second memory, when the first SVC receives the first message; andreading, by the second SVC, the data in the block of the data transmission table in the second memory. 22. The method according to claim 11, further comprising steps of: reading, by the first SVC, data in the first memory to be transmitted and transmitting the data into the data transmission table in the second memory, when the first SVC receives the first message; andreading, by the second SVC, the transmitted data in the number of block of the data transmission table in the second memory.