Information handling system with processing system, low-power processing system and shared resources
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-001/00
G06F-001/32
출원번호
US-0587048
(2012-08-16)
등록번호
US-8799695
(2014-08-05)
발명자
/ 주소
Belt, Steven L.
Sultenfuss, Andrew T.
출원인 / 주소
Dell Products, LP
대리인 / 주소
Larson Newman, LLP
인용정보
피인용 횟수 :
3인용 특허 :
43
초록▼
An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to dis
An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.
대표청구항▼
1. An information handling system comprising: a chipset including: a low power processor configured to be disabled during operation of a power processing system in the information handling system;a processor configured to be disabled during operation of a low power processing system in the informati
1. An information handling system comprising: a chipset including: a low power processor configured to be disabled during operation of a power processing system in the information handling system;a processor configured to be disabled during operation of a low power processing system in the information handling system; anda switching module, the switching module configured to enable the processor to access one or more shared resources during operation of the processing system, and configured to enable the low power processor to access one or more non-shared resources during operation of the low power processing system. 2. The information handling system of claim 1, wherein the chipset further includes: a video processing resource accessible to the processing system during operation of the processing system; andwherein the video processing resource is accessible to the low power processing system during operation of the low power processing system. 3. The information handling system of claim 1, further comprising: a power system operable to enable the processing system separate from the low power processing system, and operable to enable the low power processing system separate from the processing system. 4. The information handling system of claim 1, further comprising: a low power processing module externally coupled to the chipset;a video processing resource within the chipset and accessible to the processing system during operation of the processing system;wherein the video processing resource is accessible to the low power processing module during operation of the low power processing system and a reduced operating state of the processing system;a power subsystem of a power system configured to enable a portion of the chipset; andwherein the low power processing system is configured to access the enabled portion of the chipset to output video using the shared resource of the processing system during the reduced operating state of the processing system. 5. The information handling system of claim 1, further comprising: a video input source operably coupled to the chipset during operation of the low power processing system;a video output resource of the processing system configured to identify the video input source; andwherein the video output resource is configured to process a video input from the video input source to a display format of the display. 6. The information handling system of claim 1, wherein the chipset further includes: a power rail of a first power subsystem; anda power rail of a second power subsystem, wherein a power system of the information handling system is configured to enable the power rail of the first power subsystem and the power rail of the second power subsystem in response to an operating state of the processing system and an operating state of the low power processing system. 7. The information handling system of claim 2, wherein the video processing resource includes: a video raster coupled to the chipset and operable to be accessed as a shared video output resource; andwherein the video raster is further accessible to the low power processing system and the processing system to simultaneously output video of the low power processing system and video of the processing system to a shared video display resource. 8. The information handling system of claim 5, further comprising a power subsystem configured to enable the video output resource. 9. A chipset comprising: a low power processor configured to be disabled during operation of a processing system in an information handling system;a processor configured to be disabled during operation of a low power processing system in the information handling system;a switching module, the switching module configured to enable the processor to access one or more shared resources during operation of the processing system, and configured to enable the low power processor to access one or more non-shared resources during operation of the low power processing system; anda video multiplexing layer powered by a power system, the video multiplexing layer configured to receive a processing system video input and a low power processing system video input, and to up-scale a video output by combining the processing system video input with the low power processing system video input prior to outputting the video output. 10. The chipset of claim 9, wherein the power system is configured to enable a powering of the shared resource during operation of the processing system and operation of the low power processing system. 11. The chipset of claim 9, further comprising: a low power processor subsystem power source configured to be enabled in response to enabling the low power processor of the low power processing system separate from the processing system. 12. The chipset of claim 9, further comprising: a processor subsystem power source configured to be enabled in response to enabling the processor of the processing system separate from the low power processing system. 13. The chipset of claim 9, wherein the shared resource includes: a video display accessible to the low power processing system during operation of the low power processing system; andwherein the video display is accessible to the processing system during operation of the processing system. 14. The chipset of claim 9, wherein the chipset further includes: a power rail of a first power subsystem; anda power rail of a second power subsystem, wherein a power system of the information handling system is configured to enable the power rail of the first power subsystem and the power rail of the second power subsystem in response to an operating state of the processing system and an operating state of the low power processing system. 15. The information handling system of claim 9, wherein the chipset further includes: a power rail of a first power subsystem; anda power rail of a second power subsystem, wherein a power system of the information handling system is configured to enable the power rail of the first power subsystem and the power rail of the second power subsystem in response to an operating state of the processing system and an operating state of the low power processing system. 16. The chipset of claim 10, wherein the power system is further configured to enable the processing system separate from the low power processing system, and operable to enable the low power processing system separate from the processing system. 17. An information handling system comprising: a chipset including: a low power processor configured to be disabled during operation of a processing system in an information handling system;a processor configured to be disabled during operation of a low power processing system in the information handling system; anda switching module, the switching module configured to enable the processor to access one or more shared resources during operation of the processing system, and configured to enable the low power processor to access one or more non-shared resources during operation of the low power processing system; anda video raster coupled to the chipset and operable to be accessed as a shared video output resource by the processor and by the low power processor. 18. The information handling system of claim 17, further wherein the video raster is further accessible to the low power processing system and the processing system to simultaneously output video of the low power processing system and video of the processing system to a shared video display resource. 19. The information handling system of claim 17, further comprising: a processing system configured to access a shared resource and a non-shared resource during operation of the processing system; anda low power processing system configured to access the shared resource of the processing system during operation of the low power processing system, wherein the operation of the low power processing system is separate from operation of the processing system. 20. The information handling system of claim 17, further comprising: a control module operably coupled to the chipset and the power system to initiate powering the shared resource and the non-shared resource; anda peripheral switching module integrated within the chipset and configured to couple an output of the chipset to the shared resource during use of processing system and the low power processing system. 21. The information handling system of claim 19, further comprising: a power system configured to power the processing system, the low power processing system, the shared resource, and the non-shared resource.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (43)
Watts, Jr., La Vaughn F., Apparatus and method for a combination personal digital assistant and network portable device.
Engel Gary L. (Wyoming MN) Georgeson Paul J. (Minneapolis MN) Mueller Douglas R. (Shoreview MN) Quernemoen John M. (New Brighton MN) Todd Bruce C. (Blaine MN), Automatic power control system which automatically activates and deactivates power to selected peripheral devices based.
Hirosawa Toshio (Machida JPX) Ohki Masaru (Kodaira JPX) Kuwahara Yutaka (Hachioji JPX), Computer system with power control based on the operational status of terminals.
Kardach,James; Huckins,Jeffrey; Fleming,Kristoffer; Belmont,Brian; Hsu,Pochang; Kuchibhotla,Venu; Forand,Richard; Gadamsetty,Uma; Danneels,Gunner, Method and apparatus for a user to interface with a mobile computing device.
Rotier Michael J. (Sunnyvale CA) Huffman William A. (Santa Cruz CA), Method and apparatus for upgrading a central processing unit and existing memory structure in a computer system.
Rhoten, Matthew P.; Fuller, Andrew J.; Wynn, Roger H.; Bernstein, Michael S.; Polivy, Daniel J., Method and system for exchanging data between computer systems and auxiliary displays.
Bartley Gerald K. ; Cecchi Delbert R. ; Collett Jeffrey A. ; Herman Linda S. ; Lewis David O. ; Sellers Glenn W., Method for personalizing integrated circuit devices.
Nakashima Tatsuya,JPX, PC card capable multiple functions and corresponding card information structures (CIS) where switch setting element selects CIS to read out based on selection signal.
Kuzawinski Mark J. (Maine NY) Zielinski Edward J. (Endicott NY), Power controller for permitting multiple processors to power up shared input/output devices and inhibit power down until.
Villanueva Peter T., Power share controller for providing continuous system peripheral bay access between at least two data processing systems on a data network with no interruption to peripheral bay operation.
Polzin R. Stephen (Morgan Hill CA) Price Noah M. (Campbell CA) Takahashi Duane M. P. (San Jose CA), Printed circuit board processor card for upgrading a processor-based system.
Reed Ronald G. (Colorado Springs CO) Rasper John T. (Colorado Springs CO), Process for use in rapidly producing printed circuit boards using a computer controlled plotter.
Huber,Gary Douglas; Shoobe,Howard A.; Watts, Jr.,La Vaughn F., Removable personal digital assistant in a dual personal computer/personal digital assistant computer architecture.
Belt Steven L. (Stevensville MI) Grabon Robert J. (Berrien Springs ; Oronoko Township ; Berrien County MI) Pandya Chandrakant H. (St. Joseph MI) Sun Jiming (St. Joseph MI) Terry-Gray Neysa K. (Lake T, System suspend on lid close and system resume on lid open.
Gatson, Michael S.; Kozlowski, Joseph; Lo, Yuan-Chang; Vichare, Nikhil M., Method and apparatus for customized energy policy based on energy demand estimation for client systems.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.