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Method and system of exchanging information between processors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0042985 (2005-01-25)
등록번호 US-8799706 (2014-08-05)
발명자 / 주소
  • Bruckert, William F.
  • Garcia, David J.
  • Heynemann, Thomas A.
  • Klecka, James S.
  • Sprouse, Jeffrey A.
출원인 / 주소
  • Hewlett-Packard Development Company, L.P.
인용정보 피인용 횟수 : 0  인용 특허 : 29

초록

A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a us

대표청구항

1. A method comprising: exchanging information between a plurality of processors comprising writing, by a first processor, a first datum to a logic device, and then continuing processing of a user program by the first processor;writing, by a second processor, a second datum to the logic device, and

이 특허에 인용된 특허 (29)

  1. Clegg, Jason Alan; Graham, Charles Scott; Lambeth, Shawn Michael; Van Grinsven, Gene Steven, Apparatus and method for adaptive address-based historical utilization recording.
  2. Stanfield, McCoy J., Bag holder.
  3. Williams Emrys J., Determinism in a multiprocessor computer system and monitor and processor therefor.
  4. James Stevens Klecka ; William F. Bruckert ; Robert L. Jardine, Error self-checking and recovery using lock-step processor pair architecture.
  5. Bissett Thomas D. (Northborough MA) Fiorentino Richard D. (Carlisle MA) Glorioso Robert M. (Stow MA) McCauley Diane T. (Hopkinton MA) McCollum James D. (Whitinsville MA) Tremblay Glenn A. (Upton MA), Fault resilient/fault tolerant computing.
  6. Bissett Thomas D. ; Fitzgerald ; V Martin J. ; Leveille Paul A. ; McCollum James D. ; Muench Erik ; Tremblay Glenn A., Fault resilient/fault tolerant computing.
  7. Bissett Thomas D. ; Leveille Paul A. ; Muench Erik, Fault resilient/fault tolerant computing.
  8. Bissett Thomas Dale ; Fiorentino Richard D. ; Glorioso Robert M. ; McCauley Diane T. ; McCollum James D. ; Tremblay Glenn A. ; Troiani Mario, Fault resilient/fault tolerant computing.
  9. Bissett Thomas Dale ; Fiorentino Richard D. ; Glorioso Robert M. ; McCauley Diane T. ; McCollum James D. ; Tremblay Glenn A. ; Troiani Mario, Fault resilient/fault tolerant computing.
  10. Thomas D. Bissett ; Paul A. Leveille ; Erik Muench, Fault resilient/fault tolerant computing.
  11. Papenberg Robert L. (San Jose CA) Yang Runchan D. (San Jose CA) Wotring David H. (San Jose CA) Rydhan Mohammad F. (San Jose CA) Voloshin Paul (San Jose CA) Talaat Mohamed M. (Mountain View CA), Fault tolerant memory system.
  12. Papenberg Robert L. (San Jose CA) Yang Runchan D. (San Jose CA) Wotring David H. (San Jose CA) Rydhan Mohammad F. (San Jose CA) Voloshin Paul (San Jose CA) Talaat Mohamed M. (Mountain View CA), Fault tolerant memory system.
  13. Jewett Douglas E. (Austin TX) Bereiter Tom (Austin TX) Vetter Brian (Austin TX) Banton Randall G. (Austin TX) Cutts ; Jr. Richard W. (Georgetown TX) Westbrook ; deceased Donald C. (late of Austin TX , Fault-tolerant computer system with online recovery and reintegration of redundant components.
  14. Jewett Douglas E. ; Bereiter Tom ; Vetter Bryan ; Banton Randall G. ; Cutts ; Jr. Richard W. ; Westbrook Donald C. ; Fey ; Jr. Krayn W. ; Posdro John ; Debacker Kenneth C. ; Mehta Nikhil A., Fault-tolerant computer system with online recovery and reintegration of redundant components.
  15. Cutts ; Jr. Richard W. (Georgetown) Norwood Peter C. (Austin) DeBacker Kenneth C. (Austin) Mehta Nikhil A. (Austin) Jewett Douglas E. (Austin) Allison John D. (Austin TX) Horst Robert W. (Champaign I, Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are syn.
  16. Cutts ; Jr. Richard W. ; Debacker Kenneth C. ; Horst Robert W. ; Mehta Nikhil A. ; Jewett Douglas E. ; Allison John David ; Southworth Richard A., Interrupts between asynchronously operating CPUs in fault tolerant computer system.
  17. Bissett Thomas D. ; Leveille Paul A. ; Muench Erik ; Tremblay Glenn A., Loosely-coupled, synchronized execution.
  18. Horst Robert W. (Champaign IL), Method and apparatus for synchronizing a plurality of processors.
  19. Horst Robert W. (Cupertino CA), Method and apparatus for synchronizing a plurality of processors.
  20. Horst Robert W. (Cupertino CA), Method and apparatus for synchronizing a plurality of processors.
  21. Bissett Thomas D. (Northborough MA) Fiorentino Richard D. (Carlisle MA) Glorioso Robert M. (Stow MA) McCauley Diane T. (Hopkinton MA) McCollum James D. (Whitinsville MA) Tremblay Glenn A. (Upton MA) , Method for executing I/O request by I/O processor after receiving trapped memory address directed to I/O device from all.
  22. Sonnier David Paul ; Baker William Edward ; Bunton William Patterson ; Fowler Daniel L. ; Jones ; Jr. Curtis Willard ; Krause John C. ; Simpson Michael P. ; Watson William Joel, Method of synchronizing a pair of central processor units for duplex, lock-step operation by copying data into a corres.
  23. Kraemer Rolf (Schwieberdingen DEX) Graft Herbert (Dornstetten-Hallwangen DEX), Multi-processor system in which at least two processors access the same memory.
  24. Cutts ; Jr. Richard W. (Georgetown TX) Mehta Nikhil A. (Austin TX) Jewett Douglas E. (Austin TX), Multiple processor system having shared memory with private-write capability.
  25. Horst Robert W. (Champaign IL), Multiple-processor computer system with asynchronous execution of identical code streams.
  26. Jewett Douglas E. (Austin TX), Multiprocessor system with each processor executing the same instruction sequence and hierarchical memory providing on d.
  27. Horst Robert W. ; Garcia David J. ; Bunton William Patterson ; Bruckert William F. ; Fowler Daniel L. ; Jones ; Jr. Curtis Willard ; Sonnier David Paul ; Watson William Joel ; Williams Frank A., Self-checked, lock step processor pairs.
  28. Sonnier David P. (Austin TX) Bunton Wiliam P. (Austin TX) Cutts ; Jr. Richard W. (Georgetown TX) Klecka James S. (Lexington TX) Krause John C. (Georgetown TX) Watson William J. (Austin TX) Zalzala Li, Synchronized data transmission between elements of a processing system.
  29. Inaho Osamu,JPX, System and method for collecting dump information in a multi-processor data processing system.
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