A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first ci
A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first circuit output connected to at least one of the second transistors, and where at least one of the second transistors is connected to a device output, and where the device output includes a contact port for connection to external devices, and where at least one of the second transistors is substantially larger than at least one of the first transistors.
대표청구항▼
1. A 3D semiconductor device, comprising: a first layer comprising first transistors;a first metal layer comprising aluminum or copper overlaying said first transistors;a second layer comprising second transistors; wherein said second layer is overlying said first metal layer, andwherein said second
1. A 3D semiconductor device, comprising: a first layer comprising first transistors;a first metal layer comprising aluminum or copper overlaying said first transistors;a second layer comprising second transistors; wherein said second layer is overlying said first metal layer, andwherein said second layer thickness is less than 200 nm,a first circuit comprising at least one of said first transistors, wherein said device comprises an Electro-Static-Discharge (“ESD”) protection structure connected to at least one input structure,wherein said second layer comprises a first active portion of said ESD protection structure and said first layer comprises a second active portion of said ESD protection structure, andwherein said least one input structure is adapted to connect an input to said device from an external device. 2. A 3D semiconductor device according to claim 1, further comprising: a heat spreader layer disposed between said first layer and said second layer, anda heat removal path extending from said heat spreader layer to a top or the bottom surface of said device. 3. A 3D semiconductor device according to claim 1, wherein at least one of said second transistors comprises a back-bias region andwherein said back-bias region is constructed from an electrically conductive material with a higher than 900° C. melting temperature. 4. A 3D semiconductor device according to claim 1, further comprising: a thermal connection path extending from said second layer to a top or bottom surface of said device wherein a portion of said thermal connection path is designed to remove heat directly from at least one of said second transistors. 5. A 3D semiconductor device according to claim 1, further comprising: a first power distribution grid to provide power to said first transistors; anda second power distribution grid overlaying said second transistors, wherein said second power distribution grid has a significantly larger current carrying capacity than said first power distribution grid. 6. A 3D semiconductor device according to claim 1, further comprising: a power distribution network to provide power to said second transistors,a heat removal path extending from said power distribution network to a top or bottom surface of said device. 7. A 3D semiconductor device according to claim 1, further comprising: at least one thermally conductive and electrically non-conducting contact to said second layer to provide a heat removal path to at least one of said second transistors. 8. A 3D semiconductor device, comprising: a first layer comprising first transistors;a second layer comprising second transistors; wherein said second layer is overlying said first transistors, andwherein said second layer thickness is less than 200 nm, andwherein said second transistors are lithographically defined with less than 10 nm alignment error to said first transistors, andwherein said device comprises an Electro-Static-Discharge (“ESD”) protection structure connected to at least one input structure,wherein said second layer comprises a first active portion of said ESD protection structure and said first layer comprises a second active portion of said ESD protection structure, andwherein said least one input structure is adapted to connect an input to said device from an external device. 9. A 3D semiconductor device according to claim 8, further comprising: a first power distribution grid to provide power to said first transistors; anda second power distribution grid overlaying said second transistors, wherein said second power distribution grid has a significantly larger current carrying capacity than said first power distribution grid. 10. A 3D semiconductor device according to claim 8, further comprising: a heat removal structure designed to remove heat from at least one of said second transistors; andat least one through second layer via, wherein said heat removal structure comprises said at least one through second layer via. 11. A 3D semiconductor device according to claim 8, wherein at least one of said second transistors comprises a back-bias region andwherein said back-bias region is constructed from an electrically conductive material with a higher than 900° C. melting temperature. 12. A 3D semiconductor device according to claim 8, further comprising: a thermal connection path extending from said second layer to a top or bottom surface of said device wherein a portion of said thermal connection path is in direct contact with said second layer and is designed to remove heat directly from at least one of said second transistors. 13. A 3D semiconductor device according to claim 8, further comprising: a power distribution network to provide power to said second transistors, anda heat removal path extending from said power distribution network to a top or bottom surface of said device. 14. A 3D semiconductor device according to claim 8, further comprising: a heat spreader layer disposed between said first layer and said second layer, anda heat removal path extending from said heat spreader layer to a top or the bottom surface of said device. 15. A 3D semiconductor device according to claim 8, further comprising: at least one thermally conductive and electrically non-conducting contact to said second layer to provide a heat removal path to at least one of said second transistors. 16. A 3D semiconductor device, comprising: a first layer comprising first transistors;a first metal layer comprising aluminum or copper overlaying said first transistors; anda second layer comprising second transistors; wherein said second layer is overlying said first metal layer, andwherein said second layer thickness is less than 200 nm, andwherein said second transistors are lithographically defined with less than 10 nm alignment error to said first transistors, andwherein said device comprises an Electro-Static-Discharge (“ESD”) protection structure connected to at least one input structure,wherein said second layer comprises a first active portion of said ESD protection structure and said first layer comprises a second active portion of said ESD protection structure, andwherein said least one input structure is adapted to connect an input to said device from an external device. 17. A 3D semiconductor device according to claim 16, further comprising: at least one thermally conductive and electrically non-conducting contact to said second layer to provide a heat removal path to at least one of said second transistors. 18. A 3D semiconductor device according to claim 16, wherein at least one of said second transistors comprises a back-bias region andwherein said back-bias region is constructed from an electrically conductive material with higher than 900° C. melting temperature. 19. A 3D semiconductor device according to claim 16, further comprising: a thermal connection path for at least one of said second transistors extending from said second layer to a top or bottom surface of said device wherein a portion of said thermal connection path is in direct contact with said second layer. 20. A 3D semiconductor device according to claim 16, further comprising: a first power distribution grid to provide power to said first transistors; anda second power distribution grid overlaying said second transistors, wherein said second power distribution grid has a significantly larger current carrying capacity than said first power distribution grid. 21. A 3D semiconductor device according to claim 16, further comprising: a heat spreader layer disposed between said first layer and said second layer, anda heat removal path extending from said heat spreader layer to a top or the bottom surface of said device. 22. 3D semiconductor device according to claim 16, further comprising: a power distribution network to provide power to said second transistors, anda heat removal path extending from said power distribution network to a top or bottom surface of said device. 23. A 3D semiconductor device, comprising: a first layer comprising first transistors;a first metal layer comprising aluminum or copper overlaying said first transistors; anda second layer comprising second transistors; wherein said second layer is overlying said first metal layer, andwherein said second layer thickness is less than 200 nm, andwherein said device comprises an Electro-Static-Discharge (“ESD”) protection structure connected to at least one input structure, andwherein said second layer comprises a first active portion of said ESD protection structure, and said first layer comprises a second active portion of said ESD protection structure, andwherein said least one input structure is adapted to connect an input to said device from an external device, andwherein said first layer comprises at least one first circuit comprising said first transistors, said at least one first circuit is circumscribed by a first guard ring, andwherein said second layer comprises at least one second circuit comprising said second transistors, said at least one second circuit is circumscribed by a second guard ring, andwherein said second guard ring overlays said first guard ring. 24. 3D semiconductor device according to claim 23, further comprising: a heat removal structure designed to remove heat from at least one of said second transistors; andat least one through second layer via, wherein said heat removal structure comprises said at least one through second layer via. 25. 3D semiconductor device according to claim 23, wherein at least one of said second transistors comprises a back-bias region andwherein said back-bias region is constructed from an electrically conductive material with higher than 900° C. melting temperature. 26. 3D semiconductor device according to claim 23, further comprising: a thermal connection path extending from said second layer to a top or bottom surface of said device wherein a portion of said thermal connection path is in direct contact with said second layer and is designed to provide a heat removal path directly from at least one of said second transistors. 27. 3D semiconductor device according to claim 23, further comprising: a heat-spreader layer disposed between said first layer and said second layer; anda heat removal path extending from said heat spreader layer to a top or the bottom surface of said device. 28. 3D semiconductor device according to claim 23, further comprising: a first power distribution grid to provide power to said first transistors; anda second power distribution grid overlaying said second transistors, wherein said second power distribution grid has significantly larger current carrying capacity than said first power distribution grid. 29. 3D semiconductor device according to claim 23, further comprising: a power distribution network to provide power to said second transistors, anda heat removal path extending from said power distribution network to a top or bottom of said device. 30. 3D semiconductor device according to claim 23, further comprising: at least one thermally conductive and electrically non-conducting contact to said second layer to provide a heat removal path to at least one of said second transistors.
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Abou-Khalil, Michel J.; Gauthier, Jr., Robert J.; Lee, Tom C.; Li, Junjun; Putnam, Christopher S.; Mitra, Souvick, Design structures for high-voltage integrated circuits.
Abadeer, Wagdi W.; Chatty, Kiran V.; Gauthier, Jr., Robert J.; Rankin, Jed H.; Shi, Yun; Tonti, William R., Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures.
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Fitch Jon T. (Austin TX) Venkatesan Suresh (Austin TX) Witek Keith E. (Austin TX), Integrated circuit having both vertical and horizontal devices and process for making the same.
New,Bernard J.; Conn,Robert O.; Young,Steven P.; Young,Edel M., Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit.
Shimoto,Tadanori; Kikuchi,Katsumi; Matsui,Koji; Baba,Kazuhiro, Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device.
Vyvoda, Michael A.; Herner, S. Brad; Petti, Christopher J.; Walker, Andrew J., Inverted staggered thin film transistor with salicided source/drain structures and method of making same.
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Dawson Robert ; Fulford ; Jr. H. Jim ; Gardner Mark I. ; Hause Frederick N. ; Michael Mark W. ; Moore Bradley T. ; Wristers Derick J., Method and apparatus for in situ anneal during ion implant.
Iriguchi, Chiharu, Method for fabricating semiconductor device, and electro-optical device, integrated circuit and electronic apparatus including the semiconductor device.
Leas James Marc (South Burlington VT) Voldman Steven Howard (South Burlington VT), Method for forming a monolithic electronic module by dicing wafer stacks.
Zavracky Paul M. (Norwood MA) Zavracky Matthew (Attleboro MA) Vu Duy-Phach (Taunton MA) Dingle Brenda (Mansfield MA), Method for forming three dimensional processor using transferred thin film circuits.
Chan Kevin Kok ; D'Emic Christopher Peter ; Jones Erin Catherine ; Solomon Paul Michael ; Tiwari Sandip, Method for making bonded metal back-plane substrates.
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Harder Christoph S. (Zurich CHX) Jaeckel Heinz (Kilchberg CHX) Wolf Hans P. (Zurich CHX), Method of fabricating a self-aligned metal-semiconductor FET having an insulator spacer.
Norman Michael P. (Chandler AZ) Harvey ; III Thomas B. (Scottsdale AZ) Zhu Xiaodong T. (Chandler AZ), Method of fabricating an integrated multicolor organic led array.
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Anderson James M. (Huntington Beach CA) Coulson Andrew R. (Santa Monica CA) Demaioribus Vincent J. (Redondo Beach CA) Nicholas Henry T. (Redondo Beach CA), Method of making an adaptive configurable gate array.
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Forrest Stephen Ross ; Thompson Mark Edward ; Burrows Paul Edward ; Sapochak Linda Susan ; McCarty Dennis Matthew, Multicolor organic light emitting devices.
Forrest Stephen Ross ; Thompson Mark Edward ; Burrows Paul Edward ; Sapochak Linda Susan ; McCarty Dennis Matthew, Multicolor organic light emitting devices.
Forrest Stephen Ross ; Thompson Mark Edward ; Burrows Paul Edward ; Sapochak Linda Susan ; McCarty Dennis Matthew, Multicolor organic light emitting devices.
Jang, Jae Hoon; Jung, Soon Moon; Kim, Jong Hyuk; Rah, Young Seop; Park, Han Byung, Non-volatile memory devices including etching protection layers and methods of forming the same.
Koh, Gwan-Hyeob; Ha, Dae-Won, Non-volatile memory devices including stacked NAND-type resistive memory cell strings and methods of fabricating the same.
Kim, Sarah E.; List, R. Scott; Kellar, Scot A., Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices.
Kim,Sarah E.; List,R. Scott; Kellar,Scot A., Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices.
Breitwisch, Matthew J.; Ditlow, Gary S.; Franceschini, Michele M.; Lastras-Montano, Luis A.; Montoye, Robert K.; Rajendran, Bipin, Resistive memory devices having a not-and (NAND) structure.
Thomas, Olivier; Batude, Perrine; Pouydebasque, Arnaud; Vinet, Maud, SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable.
Nemati Farid ; Plummer James D., Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches.
Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Semiconductor component having plate, stacked dice and conductive vias.
Saito Keishi (Nabari JPX) Fujioka Yasushi (Ueno JPX), Semiconductor device having a semiconductor region in which a band gap being continuously graded.
Mazur Carlos A. (Austin TX) Fitch Jon T. (Austin TX) Hayden James D. (Austin TX) Witek Keith E. (Austin TX), Semiconductor memory device and method of formation.
Zavracky Paul M. (Norwood MA) Fan John C. C. (Chestnut Hill MA) McClelland Robert (Norwell MA) Jacobsen Jeffrey (Hollister CA) Dingle Brenda (Norton MA) Spitzer Mark B. (Sharon MA), Single crystal silicon arrayed devices for display panels.
Iyer Subramanian S. ; Baran Emil ; Mastroianni Mark L. ; Craven Robert A., Single-etch stop process for the manufacture of silicon-on-insulator wafers.
Atkinson Gary M. (1012 - 7th St. ; #15 Santa Monica CA 90403) Courtney M. DuChesne (15127 Blackhawk Mission Hills CA 91345), Split collector vacuum field effect transistor.
Schuehrer,Holger; Hartig,Carsten; Bartsch,Christin; Frohberg,Kai, Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer.
Barbee Steven G. (Dover Plains NY) Leas James M. (Washington DC) Lloyd James R. (Fishkill NY) Nagarajan Arunachala (Wappingers Falls NY), Thin film semiconductor device and method for manufacture.
Chan, Victor; Guarini, Kathryn W.; Ieong, Meikei, Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers.
Alam, Syed M.; Elfadel, Ibrahim M.; Guarini, Kathryn W; Ieong, Meikei; Kudva, Prabhakar N.; Kung, David S.; Lavin, Mark A.; Rahman, Arifur, Three dimensional integrated circuit and method of design.
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Titus, Jeffrey L.; Savage, Mark; Cole, Patrick L.; Duncan, Adam R., Combination metal oxide semi-conductor field effect transistor (MOSFET) and junction field effect transistor (JFET) operable for modulating current voltage response or mitigating electromagnetic or radiation interference effects by altering current flow through the MOSFETs semi-conductive channel region (SCR).
Samadi, Kambiz; Panth, Shreepad Amar; Kamal, Pratyush; Du, Yang, Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace.
Xie, Jing; Du, Yang, Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods.
Xie, Jing; Du, Yang, Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICs), 3DIC processor cores, and methods.
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