A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from t
A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.
대표청구항▼
1. A data processor chip comprising: a plurality of data processing elements each including at least one arithmetic-logic-unit;a plurality of memory elements adapted for storing at least one of program data and program code;at least one input/output element adapted for transmitting data to and recei
1. A data processor chip comprising: a plurality of data processing elements each including at least one arithmetic-logic-unit;a plurality of memory elements adapted for storing at least one of program data and program code;at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals; anda bus system;wherein: each of the data processing, memory, and input/output elements is dedicated to its respective function and separate from each other;the bus system interconnects the data processing, memory, and input/output elements for transmitting data between specific ones of the elements according to a setting of the bus system at runtime; andeach of the data processing, memory, and input/output elements is flexibly connectable for transmitting data to at least one other of the data processing, memory, and input/output elements depending on the setting of the bus system at runtime. 2. A data processor chip comprising: a plurality of data processing elements each including at least one arithmetic-logic unit;a plurality of memory elements adapted for storing at least one of program data and program code;at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals; anda bus system;wherein each of the data processing, memory, and input/output elements is dedicated to its respective function and separate from each other;the bus system interconnects the data processing, memory, and input/output elements for transmitting data between specific ones of the elements according to a setting of the bus system; andeach of the data processing, memory, and input/output elements is adapted for transmitting data to at least one other of the data processing, memory, and input/output elements depending on the setting of the bus system. 3. A computer system including: a data processor chip having a plurality of data processing elements each including at least one arithmetic-logic unit;a plurality of memory elements adapted for storing at least one of program data and program code;at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals; anda bus system;wherein each of the data processing, memory, and input/output elements is dedicated to its respective function and separate from each other;the bus system interconnects the data processing, memory, and input/output elements for transmitting data between specific ones of the elements according to a setting of the bus system; andeach of the data processing, memory, and input/output elements is adapted for transmitting data to at least one other of the data processing, memory, and input/output elements depending on the setting of the bus system. 4. A computer system including: a plurality of data processing elements each including an arithmetic-logic unit;a plurality of memory elements adapted for storing at least one of program data and program code;at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals; anda bus system;wherein each of the data processing, memory, and input/output elements is separate from the others of the data processing, memory and input/output elements, and each of the data processing, memory, and input/output elements is adapted specifically to perform respectively the functions of data processing, memory storage, and input/output; andthe bus system interconnects the data processing, memory, and input/output elements such that specific pairs of the elements are interconnected depending upon a setting of the bus system.
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Bock Gnther (Kmmersbruck DEX) Macht Helmut (Kmmersbruck DEX) Wombacher Christof (Amberg DEX) Prechtl Manfred (Nabburg DEX) Lengemann Andre (Edelsfeld DEX), Programmable control system including a logic module and a method for programming.
Flood Mark A. (1330 Worton Blvd. Mayfield Heights OH 44124) White Clay T. (26151 Lakeshore Blvd. ; #1220 Euclid OH 44132), Programmable controller with time periodic communication.
Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX), Programmable digital signal processor for performing a plurality of signal processings.
Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array device having cascaded means for function definition.
Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array with improved interconnect structure, input/output structure and configurable logic block.
Yamaura Shinichi (Takarazuka JPX) Yasui Takashi (Toyonaka JPX) Yoshioka Keiichi (Sanda JPX), Programmable logic array and data processing unit using the same.
Leong William W. (San Francisco CA) Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA), Programmable logic array device with grouped logic regions and three types of conductors.
Lytle Craig S. (Mountain View CA) Faria Donald F. (San Jose CA), Programmable logic array integrated circuit incorporating a first-in first-out memory.
Cliff Richard G. (Milpitas CA) Cope L. Todd (San Jose CA) McClintock Cameron R. (Mountain View CA) Leong William (San Fransisco CA) Watson James A. (Santa Clara CA) Huang Joseph (San Jose CA) Ahanin , Programmable logic array integrated circuits.
Cliff Richard G. ; Cope L. Todd ; McClintock Cameron ; Leong William ; Watson James Allen ; Huang Joseph ; Ahanin Bahram ; Sung Chiakang ; Chang Wanli, Programmable logic array integrated circuits.
Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA) Leong William (San Francisco CA), Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks.
Pedersen Bruce B. (Santa Clara CA) Cliff Richard G. (Santa Clara CA) Ahanin Bahram (Cupertino CA) Lytle Craig S. (Palo Alto CA) Heile Francis B. (Santa Clara CA) Veenstra Kerry S. (Concord CA), Programmable logic array with local and global conductors.
Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array.
Jefferson David E. ; McClintock Cameron ; Schleicher James ; Lee Andy L. ; Mejia Manuel ; Pedersen Bruce B. ; Lane Christopher F. ; Cliff Richard G. ; Reddy Srinivas T., Programmable logic device architecture with super-regions having logic regions and a memory region.
Ahanin Bahram (Cupertino CA) Balicki Janusz K. (San Jose CA) Kiani Khusrow (Oakland CA) Leong William (San Francisco CA) Li Ken-Ming (Santa Clara CA) Nouban Bezhad (Fremont CA), Programmable logic device having fast programmable logic array blocks and a central global interconnect array.
Hung Lawrence C. (Los Gatos CA) Erickson Charles R. (Fremont CA), Programmable logic device including a parallel input device for loading memory cells.
Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device with hierarchical confiquration and state storage.
New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundarajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
John K. Gee ; David A. Greve ; David S. Hardin ; Allen P. Mass ; Michael H. Masters ; Nick M. Mykris ; Matthew M. Wilding, Real time processor capable of concurrently running multiple independent JAVA machines.
Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining proc.
Blackborow Richard J. (Cupertino CA) Hahn Peter S. (Fremont CA) Camp Claude E. (Milpitas CA) Westwood Donald C. (Cupertino CA) Florea Rodica (San Jose CA) Botto Eric J. (Palo Alto CA) Richmond Scott , Removable and transportable hard disk subsystem.
McGee Cindy R. ; Hester Garyl L. ; DeNardo John ; Hester Kenneth W. ; Gibbons Tami J. ; Staff Bradley J., Resource type prioritization in generating a device configuration.
Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Retter E, SIMD/MIMD processing memory element (PME).
Hansen Siegfried (Los Angeles CA) Grinberg Jan (Los Angeles CA) Etchells Robert D. (Topanga CA), Segregator functional plane for use in a modular array processor.
Pechanek Gerald G. (Cary NC) Larsen Larry D. (Raleigh NC) Glossner Clair John (Durham NC) Vassiliaadis Stamatis (Zoetermeer NLX) McCabe Daniel H. (Chapel Hill NC), Selective processing and routing of results among processors controlled by decoding instructions using mask value derive.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Sequencer for a time multiplexed programmable logic device.
Saito Miyoshi,JPX ; Ogawa Junji,JPX, Signal transmission system using PRD method, receiver circuit for use in the signal transmission system, and semiconductor memory device to which the signal transmission system is applied.
Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Slide bus communication functions for SIMD/MIMD array processor.
Zandveld Frederik (Hulsberg NLX) Wendt Matthias (Wurselen DEX) Janssens Marcel D. (Palo Alto CA), Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRA.
Larson Ronald J. (Minneapolis MN), State machine having a variable timing mechanism for varying the duration of logical output states of the state machine.
Phillips James E. (Binghamton NY) Blaner Bartholomew (Newark Valley NY) Vassiliadis Stamatis (Vestal NY), Status predictor for combined shifter-rotate/merge unit.
Veytsman Isaak ; Seltzer Jeffrey H., Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation struct.
Mark J. Foster ; Saifuddin T. Fakhruddin ; James L. Walker ; Matthew B. Mendelow ; Jiming Sun ; Rodman S. Brahman ; Michael P. Krau ; Brian D. Willoughby ; Michael D. Maddix ; Steven L. Belt, Suspend/resume capability for a protected mode microprocesser.
Feeney James W. (Endicott NY) Jabusch John D. (Endwell NY) Lusch Robert F. (Vestal NY) Olnowich Howard T. (Endwell NY) Wilhelm ; Jr. George W. (Endwell NY), Switch network extension of bus architecture.
Yamada, Akira, Synchronous signal producing circuit for controlling a data ready signal indicative of end of access to a shared memory and thereby controlling synchronization between processor and coprocessor.
Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization.
Wygodny Shlomo,ILX ; Barboy Dmitry,ILX ; Prouss Georgi,UAX ; Vorobey Anatoly,ILX, System and method for monitoring and analyzing the execution of computer programs.
Songer,Christopher; Eslick,Ian S.; French,Robert S., System and method for preparing software for execution in a dynamically configurable hardware environment.
Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.
Pitts William M. (780 Mora Dr. Los Altos CA 94024), System for accessing distributed data cache channel at each network node to pass requests and data.
Rubinstein Jon (Palo Alto CA) Klingman Kenneth C. (Portola CA), System for assigning interrupts to least busy processor that already loaded same class of interrupt routines.
Loyer Bruce A. ; Pham Thai H. ; Spilo David A., System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again.
Sluijter Robert J. (Eindhoven NLX) Huizer Cornelis M. (Eindhoven NLX) Dijkstra Hendrik (Eindhoven NLX), System with plurality of processing elememts each generates respective instruction based upon portions of individual wor.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.
Frankle Jon A. (San Jose CA) Chene Mon-Ren (Cupertino CA), Timing driven method for laying out a user\s circuit onto a programmable integrated circuit device.
Wise Adrian P.,GBX ; Dewar Kevin D.,GBX ; Jones Anthony Mark,GBX ; Sotheran Martin William,GBX ; Smith Colin,GBX ; Finch Helen Rosemary,GBX ; Claydon Anthony Peter John,GBX ; Patterson Donald William, Token-based adaptive video processing arrangement.
Selvidge Charles W. (Charlestown MA) Dahl Matthew L. (Cambridge MA), Transition analysis and circuit resynthesis method and device for digital circuit modeling.
Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.
Schmidt Ulrich (Freiburg DEX) Caesar Knut (Gundelfingen DEX), Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake.
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