IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
|
| 국제특허분류(IPC7판) |
|
| 출원번호 |
US-0828166
(2010-06-30)
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| 등록번호 |
US-8810028
(2014-08-19)
|
|
발명자
/ 주소 |
- Zohni, Nael
- Nagarajan, Kumar
- Boja, Ronilo
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| 출원인 / 주소 |
|
| 대리인 / 주소 |
|
| 인용정보 |
피인용 횟수 :
0 인용 특허 :
107 |
초록
▼
Integrated circuit packaging devices and methods are disclosed. An embodiment package lid is formed from a single piece of material. The lid includes a planar rectangular main body having a bottom surface, and a leg disposed at each corner of the main body and within a perimeter of the main body. Ea
Integrated circuit packaging devices and methods are disclosed. An embodiment package lid is formed from a single piece of material. The lid includes a planar rectangular main body having a bottom surface, and a leg disposed at each corner of the main body and within a perimeter of the main body. Each leg has a wall projecting downwardly from the main body and a non-planar bottom surface disposed at a bottom of the wall. The non-planar bottom surface of the leg faces a same direction as the main body bottom surface.
대표청구항
▼
1. An integrated circuit package comprising: a package substrate having an array of top electrical contacts disposed on its top surface, and an array of bottom electrical contacts disposed on its bottom surface;a semiconductor die disposed on the package substrate, the semiconductor die having an ar
1. An integrated circuit package comprising: a package substrate having an array of top electrical contacts disposed on its top surface, and an array of bottom electrical contacts disposed on its bottom surface;a semiconductor die disposed on the package substrate, the semiconductor die having an array of die electrical contacts disposed on its bottom surface, wherein the die electrical contacts are bonded to the package substrate top electrical contacts by a first ball grid array, and wherein a perimeter of the semiconductor die is spaced inwardly from a perimeter of the package substrate such that a perimeter region of the package substrate is not covered by the semiconductor die;a lid having a planar main body disposed on the semiconductor die, and having legs located at corners of the main body disposed on corners of the perimeter region of the package substrate, wherein each of the legs has a non-planar, multi-faceted bottom surface that is divided into a plurality of portions, each of the plurality of portions having a plurality of planes which is not parallel with the main body and extends from an outer edge of the leg toward a center of the leg, wherein the plurality of portions are formed at adjacent side portions of the leg at a corner of the perimeter region of the package substrate, the legs forming openings between adjacent legs on each side of the integrated circuit package and extending from the main body to the package substrate, and wherein a perimeter of the lid main body extends over sides of the perimeter region between the corners of the perimeter region;an inelastic adhesive mechanically attaching the non-planar, multi-faceted bottom surface of each lid leg to the perimeter region of the package substrate; anda thermal interface material disposed between and thermally coupling a bottom surface of the lid main body and a top surface of the semiconductor die. 2. The integrated circuit package of claim 1, wherein the lid is a stamped single sheet of material comprising at least one metal. 3. The integrated circuit package of claim 1, wherein the inelastic adhesive is an epoxy-based material. 4. The integrated circuit package of claim 1, further comprising an underfill material disposed between the bottom surface of the semiconductor die and the top surface of the package substrate. 5. The integrated circuit package of claim 1, further comprising a passive component disposed on one of the sides of the perimeter region, and under the main body of the lid. 6. The integrated circuit package of claim 1, wherein the package substrate is a printed circuit board. 7. The integrated circuit package of claim 1, further comprising a second ball grid array disposed on the array of bottom electrical contacts on the bottom surface of the package substrate. 8. The integrated circuit package of claim 1, wherein the inelastic adhesive has a modulus greater than about 1.0 GPa. 9. An integrated circuit package lid comprising: a planar rectangular main body having a bottom surface; anda leg disposed at each corner of the main body and within a perimeter of the main body, wherein each leg has a wall projecting downwardly from the main body, wherein each leg has a non-planar, multi-faceted bottom surface disposed at a bottom of the wall and divided into a plurality of portions, each of the plurality of portions having a plurality of planes which is not parallel with the main body and extends from an outer edge of the leg toward a center of the leg, wherein the plurality of portions are formed at adjacent side portions of the leg at a corner of the leg, the legs forming openings between adjacent legs on each side of the integrated circuit package lid, and wherein the non-planar, multi-faceted bottom surface faces a same direction as the main body bottom surface, and wherein the lid is a single piece of material comprising the main body and legs. 10. The integrated circuit package lid of claim 9, wherein the non-planar, multi-faceted bottom surface of the legs comprises a series of ridges. 11. The integrated circuit package lid of claim 9, wherein the lid is single piece of stamped material comprising at least one metal. 12. The integrated circuit package lid of claim 9, wherein the lid is single piece of milled material comprising at least one metal. 13. The integrated circuit package lid of claim 9, wherein the lid comprises a material selected from the group consisting of: nickel, copper, aluminum, and combinations thereof. 14. The integrated circuit package of claim 1, wherein the plurality of portions comprises a plurality of quarter portions. 15. The integrated circuit package of claim 14, wherein each quarter portion of the plurality of quarter portions includes 2 non-parallel planes of the plurality of planes.
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