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Multi-layer interconnect structure for stacked dies 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-021/768
  • H01L-021/683
  • H01L-023/00
  • H01L-023/525
출원번호 US-0608456 (2012-09-10)
등록번호 US-8841773 (2014-09-23)
발명자 / 주소
  • Chang, Hung-Pin
  • Chiu, Chien-Ming
  • Wu, Tsang-Jiuh
  • Shue, Shau-Lin
  • Yu, Chen-Hua
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
    Slater and Matsil, L.L.P.
인용정보 피인용 횟수 : 2  인용 특허 : 83

초록

A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconduct

대표청구항

1. A semiconductor device comprising: a first substrate;a through-substrate via comprising a single continuous structure extending from a first side of the first substrate through the first substrate and protruding from a second side of the first substrate by a first distance, the through-substrate

이 특허에 인용된 특허 (83)

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이 특허를 인용한 특허 (2)

  1. Chang, Hung-Pin; Hsu, Kuo-Ching; Chen, Chen-Shien; Chiou, Wen-Chih; Yu, Chen-Hua, Bump structure for stacked dies.
  2. Lee, Ho-Jin; Lee, Kyu-ha; Choi, Gilheyun; Choi, YongSoon; Kang, Pil-Kyu; Park, Byung-Lyul; Chung, Hyunsoo, Semiconductor devices having conductive via structures and methods for fabricating the same.
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