Method and system for high speed options pricing
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06Q-040/00
G06Q-040/04
G06Q-040/06
출원번호
US-0912354
(2010-10-26)
등록번호
US-8843408
(2014-09-23)
발명자
/ 주소
Singla, Naveen
Parsons, Scott
Franklin, Mark A.
Taylor, David E.
출원인 / 주소
IP Reservoir, LLC
대리인 / 주소
Thompson Coburn LLP
인용정보
피인용 횟수 :
9인용 특허 :
244
초록▼
A high speed technique for options pricing in the financial industry is disclosed that can provide both high throughput and low latency. Parallel/pipelined architectures are disclosed for computing an option's theoretical fair price. Preferably these parallel/pipelined architectures are deployed in
A high speed technique for options pricing in the financial industry is disclosed that can provide both high throughput and low latency. Parallel/pipelined architectures are disclosed for computing an option's theoretical fair price. Preferably these parallel/pipelined architectures are deployed in hardware, and more preferably reconfigurable logic such as Field Programmable Gate Arrays (FPGAs) to accelerate the options pricing operations relative to conventional software-based options pricing operations.
대표청구항▼
1. An apparatus for computing a price for an option, the apparatus comprising: at least one member of the group consisting of a reconfigurable logic device, a graphics processor unit (GPU), and a chip multi-processor;the at least one member having an options pricing engine deployed thereon, the at l
1. An apparatus for computing a price for an option, the apparatus comprising: at least one member of the group consisting of a reconfigurable logic device, a graphics processor unit (GPU), and a chip multi-processor;the at least one member having an options pricing engine deployed thereon, the at least one member configured to receive a data stream comprising financial market data, the financial market data comprising a plurality of data messages corresponding to a plurality of options on at least one underlying financial instrument, the data messages comprising data that describes the options, wherein the at least one member comprises a plurality of parallel computational units, each of the plurality of parallel computational units configured to (1) receive a volatility value and a portion of the data stream representative of a particular option, (2) compute a theoretical fair market price for the particular option based on the received volatility value, and (3) provide the computed theoretical fair market price as an output such that the plurality of parallel computational units are configured to simultaneously compute a plurality of theoretical fair market prices. 2. The apparatus of claim 1 wherein at least one of the parallel computational units comprises a plurality of pipelined stages that are configured to operate in a pipelined manner as the financial market data streams through the at least one member, a plurality of the pipelined stages comprising a plurality of parallel computational nodes, each of the computational nodes being configured to compute a step of a stepwise option pricing model, and wherein the computational nodes are cascaded such that each successive pipelined stage is configured to receive as its input the output from at least two computational nodes in the immediately preceding pipelined stage, wherein the output of the last pipelined stage comprises the computed theoretical fair market price for the particular option. 3. The apparatus of claim 2 wherein the pipelined stages are arranged in a binomial tree of computational nodes, wherein the tree is of depth n. 4. The apparatus of claim 3 wherein the at least one member is configured to partition the binomial tree across a plurality of processing resources. 5. The apparatus of claim 4 wherein the plurality of processing resources comprise processing resources of different types. 6. The apparatus of claim 2 wherein the at least one member comprises a reconfigurable logic device. 7. The apparatus of claim 2 wherein the at least one member comprises a graphics processor unit (GPU). 8. The apparatus of claim 2 wherein the at least one member comprises a chip multi-processor. 9. The apparatus of claim 1 wherein at least one of the parallel computational units comprises a first set of pipelined stages that are configured to operate in a pipelined manner as the financial market data streams through the at least one member, wherein the first set of pipelined stages are configured to compute a plurality of financial instrument prices according to an option pricing model based on an upward multiplicative factor and a downward multiplicative factor, the upward multiplicative factor and the downward multiplicative factor being functions of the received volatility value. 10. The apparatus of claim 9 wherein the at least one parallel computational unit further comprises a second set of the pipelined stages that are configured to operate in a pipelined manner as the financial market data streams through the at least one member, wherein the second set of pipelined stages are configured to compute a plurality of probability terms according to the option pricing model, wherein the plurality of probability terms are used in the theoretical fair market price computation. 11. The apparatus of claim 10 wherein the first set and the second set of pipelined stages are arranged in parallel with each other. 12. The apparatus of claim 10 further comprising a combinatorial logic stage downstream from the first set and the second set of pipelined stages, wherein the combinatorial logic stage is configured to compute the theoretical fair market price for the particular option based on a plurality of terminal financial instrument prices computed by the first set of pipelined stages and a plurality of terminal computed probability terms from the second set of pipelined stages. 13. The apparatus of claim 9 wherein the at least one member comprises a reconfigurable logic device. 14. The apparatus of claim 9 wherein the at least one member comprises a graphics processor unit (GPU). 15. The apparatus of claim 9 wherein the at least one member comprises a chip multi-processor. 16. The apparatus of claim 1 wherein the at least one member comprises a lookup table, the lookup table configured to store a plurality of precomputed terms for use in the theoretical fair market price computation, and wherein at least one of the parallel computational units is configured to, for each of a plurality of the options, (1) retrieve precomputed terms from the lookup table using an index based at least in part upon a volatility for the underlying financial instrument for the particular option, and (2) compute the theoretical fair market price for the particular option based at least in part on the retrieved precomputed terms. 17. The apparatus of claim 16 wherein the lookup table comprises (1) a first lookup table in which a plurality of volatility values for a plurality of different financial instruments are stored, wherein the first lookup table is indexed by financial instrument, and (2) a second lookup table in which the plurality of precomputed terms are stored, wherein the second lookup table is indexed by a volatility for the underlying financial instrument and a time to maturity for the option; and wherein the at least one parallel computational unit comprises (1) a lookup unit that is configured to (i) process the data describing the option, the data describing the option comprising an identifier for the underlying financial instrument and a time to maturity for the option, (ii) access the first lookup table based on an identity of the underlying financial instrument for the option to thereby retrieve the volatility value for that underlying financial instrument, and (iii) access the second lookup table based on the retrieved volatility value and a time to maturity for the option to thereby retrieve the plurality of precomputed terms applicable to that option; anda combinatorial logic stage that is configured to compute the theoretical fair market price according to an option pricing model based at least in part upon the data describing the option, the retrieved volatility value and the retrieved precomputed terms. 18. The apparatus of claim 17 wherein the combinatorial logic stage comprises a plurality of parallel computational pipelines and an adder downstream from the parallel computational pipelines, wherein each computational pipeline is configured to compute, in parallel with the other parallel computational pipelines, a subcomponent of the theoretical fair market price based at least in part upon the data describing the option, the retrieved volatility value and the retrieved precomputed terms, and wherein the adder is configured to compute the theoretical fair market price for the option by summing the computed subcomponents produced by the parallel computational pipelines. 19. The apparatus of claim 16 wherein the at least one member comprises a reconfigurable logic device. 20. The apparatus of claim 16 wherein the at least one member comprises a graphics processor unit (GPU). 21. The apparatus of claim 16 wherein the at least one member comprises a chip multi-processor. 22. The apparatus of claim 1 wherein the data describing the options comprises a flag for identifying whether a subject option is a call option or a put option, wherein at least one of the parallel computational units comprises a first computational path configured to compute a theoretical fair market price for a call option and a second computational path configured to compute a theoretical fair market price for a put option, and wherein the at least one parallel computational units is further configured to selectively route data describing the options to the first or second computational path based on the flag for the subject option. 23. The apparatus of claim 1 wherein the at least one member further comprises a plurality of pipelined computational modules for computing an implied volatility for each of a plurality of options over a plurality of iterations, wherein each computational module in the pipeline corresponds to a different iteration of the implied volatility computation such that the computational modules in the pipeline are configured to simultaneously perform different iterations of the implied volatility computation for different options, each pipelined computational module comprising at least two of the parallel computational units. 24. The apparatus of claim 23 wherein the parallel computational units circuits of a computational module are seeded with different volatility values, wherein the parallel computational units of the computational module corresponding to a first iteration of the implied volatility computation are configured to compute a plurality of theoretical fair market prices for a band of volatility values, and wherein the parallel computational units of the computational modules corresponding to subsequent iterations of the implied volatility computation are configured to compute a plurality of theoretical fair market prices for progressively narrower bands of volatility values. 25. The apparatus of claim 23 wherein the at least one member comprises a reconfigurable logic device. 26. The apparatus of claim 23 wherein the at least one member comprises a graphics processor unit (GPU). 27. The apparatus of claim 23 wherein the at least one member comprises a chip multi-processor. 28. The apparatus of claim 1 further comprising a processor in communication with the at least one member, the processor configured to deliver the financial market data stream to the at least one member. 29. The apparatus of claim 28 wherein the at least one member comprises a reconfigurable logic device. 30. The apparatus of claim 28 wherein the at least one member comprises a graphics processor unit (GPU). 31. The apparatus of claim 28 wherein the at least one member comprises a chip multi-processor. 32. The apparatus of claim 1 further comprising a processor configured to execute a black box trading algorithm, and wherein the at least one member is further configured to feed a computed theoretical fair market price for an option to the processor, and wherein the processor is further configured to automatically generate a financial instrument trade via the black box trading algorithm based at least in part upon the computed theoretical fair market price for the option. 33. The apparatus of claim 1 further comprising a processor in communication with the at least one member, wherein the at least one member serves as an offload engine relative to the processor, the at least one member being a computational resource separate from the processor. 34. The apparatus of claim 33 wherein the processor comprises a general purpose processor (GPP) configured to execute software to manage an interface with the at least one member. 35. The apparatus of claim 1 wherein the at least one member comprises a reconfigurable logic device. 36. The apparatus of claim 1 wherein the at least one member comprises a graphics processor unit (GPU). 37. The apparatus of claim 1 wherein the at least one member comprises a chip multi-processor. 38. A method for computing a price for an option, the method comprising: processing, by at least at least one member of the group consisting of a reconfigurable logic device, a graphics processor unit (GPU), and a chip multi-processor, an electronic data stream comprising financial market data, the financial market data comprising a plurality of data messages corresponding to a plurality of options on at least one underlying financial instrument, the data messages comprising data that describes the options, wherein the at least one member comprises a plurality of parallel computational units; andwherein the processing step comprises each of the parallel computational units (1) receiving a volatility value and a portion of the data stream representative of a particular option, (2) computing a theoretical fair market price for the particular option based on the received volatility value, and (3) providing the computed theoretical fair market price as an output such that the plurality of parallel computational units simultaneously compute a plurality of theoretical fair market prices. 39. The method of claim 38 wherein the at least one member comprises a reconfigurable logic device. 40. The method of claim 38 wherein the at least one member comprises a graphics processor unit (GPU). 41. The method of claim 38 wherein the at least one member comprises a chip multi-processor. 42. The method of claim 38 wherein the at least one member further comprises a pipeline, the pipeline comprising a plurality of computational modules arranged in a pipelined manner for computing a plurality of implied volatilities for a plurality of options based on at least a portion of the financial market data, each computational module comprising at least two of the parallel computational units; wherein the processing step further comprises the pipeline computing each implied volatility based on the theoretical fair market prices computed by the parallel computational units using an iterative banded search within a volatility space for an option described by the data stream to identify a volatility value that serves as the implied volatility for an option; andwherein the implied volatility computing step comprises: each computational module operating in the pipelined manner such that each computational module performs a different iteration of the iterative banded search;each downstream computational module performing its iteration of the iterative banded search within a narrower band of volatility with respect to an option than its upstream neighboring computational module in the pipeline did with respect to that option; andthe computational modules operating simultaneously as the financial market data streams through the pipeline such that each downstream computational module in pipeline performs its iteration of the iterative banded search with respect to an option while its upstream neighboring computational module in the pipeline performs its iteration of the iterative banded search for another option. 43. The method of claim 42 wherein the at least one member comprises a reconfigurable logic device. 44. The method of claim 42 wherein the at least one member comprises a graphics processor unit (GPU). 45. The method of claim 42 wherein the at least one member comprises a chip multi-processor.
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