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다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
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Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0902606 (2013-05-24) |
등록번호 | US-8846463 (2014-09-30) |
발명자 / 주소 |
|
출원인 / 주소 |
|
인용정보 | 피인용 횟수 : 2 인용 특허 : 331 |
A method to construct a semiconductor device, the method including: forming a first mono-crystallized semiconductor layer; forming a second mono-crystallized semiconductor layer including mono-crystallized semiconductor transistors; where the second mono-crystallized semiconductor layer overlays the
A method to construct a semiconductor device, the method including: forming a first mono-crystallized semiconductor layer; forming a second mono-crystallized semiconductor layer including mono-crystallized semiconductor transistors; where the second mono-crystallized semiconductor layer overlays the first mono-crystallized semiconductor layer, where the first mono-crystallized semiconductor layer includes an alignment mark and the transistors are aligned to the alignment mark, and where the first mono-crystallized semiconductor layer includes logic circuits, and connecting the logic circuits to an external device using input/output (I/O) circuits, where the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.
1. A method to construct a semiconductor device, the method comprising: forming a first layer comprising mono-crystallized semiconductor and first logic circuits;forming a second layer comprising a mono-crystallized semiconductor layer, said second layer overlying said first logic circuits;forming t
1. A method to construct a semiconductor device, the method comprising: forming a first layer comprising mono-crystallized semiconductor and first logic circuits;forming a second layer comprising a mono-crystallized semiconductor layer, said second layer overlying said first logic circuits;forming transistors on said second layer; wherein said forming transistors comprises a lithography step, said lithography step comprises an alignment to said first layer, andconnecting said first logic circuits to an external device using input/output (I/O) circuits, said input/output (I/O) circuits are constructed on said second mono-crystallized semiconductor layer. 2. The method according to claim 1, wherein said first logic circuits comprise copper or aluminum interconnect, andwherein a plurality of said transistors are connected to form second logic circuits. 3. The method according to claim 1, wherein said first logic circuits comprises copper or aluminum interconnect, andwherein at least one of said transistors is a horizontally oriented transistor. 4. The method according to claim 1, further comprising: etching at least a portion of said transistors in a customization step of a generic structure. 5. The method according to claim 1, wherein said semiconductor device comprises a circuit that provides a wireless connection to a device that is external to said semiconductor device. 6. The method according to claim 1, wherein said forming transistors comprises optical annealing. 7. The method according to claim 1, wherein said forming transistors comprises gate replacement. 8. A method to construct a semiconductor device, the method comprising: forming a first layer comprising mono-crystallized semiconductor and first logic circuits;forming a second layer comprising a mono-crystallized semiconductor layer, said second layer overlying said first logic circuits;forming transistors on said second layer; wherein said forming transistors comprises a lithography step, said lithography step comprises an alignment to said first layer, andconnecting said first logic circuits to an external device using input/output (I/O) circuits, said input/output (I/O) circuits are constructed on said second mono-crystallized semiconductor layer, wherein said input/output (I/O) circuits comprise a SerDes circuit. 9. The method according to claim 8, wherein said first logic circuits comprise copper or aluminum interconnect, andwherein a plurality of said transistors are connected to form second logic circuits. 10. The method according to claim 8, wherein said semiconductor device comprises a circuit that provides a wireless connection to a device that is external to said semiconductor device. 11. The method according to claim 8, further comprising: etching at least a portion of said transistors in a customization step of a generic structure. 12. The method according to claim 8, wherein said connecting comprises applying at least one Through Silicon Via (TSV). 13. The method according to claim 8, wherein said forming transistors comprises optical annealing. 14. The method according to claim 8, wherein said forming transistors comprises gate replacement. 15. A method to construct a semiconductor device, the method comprising: forming a first layer comprising mono-crystallized semiconductor and first logic circuits;forming a second layer comprising a mono-crystallized semiconductor layer, said second layer overlying said first logic circuits;forming transistors on said second layer; wherein said forming transistors comprises a lithography step, said lithography step comprises an alignment to said first layer,wherein said transistors are connected to form second logic circuits, andwherein said second logic circuits comprise a scan chain. 16. The method according to claim 15, wherein said first logic circuits comprise copper or aluminum interconnect. 17. The method according to claim 15, wherein said first logic circuits comprises copper or aluminum interconnect, andwherein at least one of said transistors is a horizontally oriented transistor. 18. The method according to claim 15, further comprising: etching at least a portion of said transistors in a customization step of a generic structure. 19. The method according to claim 15, wherein said semiconductor device comprises a circuit that provides a wireless connection to an external device. 20. The method according to claim 15, further comprising: connecting said first logic circuits to an external device using input/output (I/O) circuits, said input/output (I/O) circuits are constructed on said second mono-crystallized semiconductor layer. 21. The method according to claim 15, wherein said forming transistors comprises gate replacement.
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