Multi-core electronic system having a rate adjustment module for setting a minimum transmission rate that is capable for meeting the total bandwidth requirement to a shared data transmission interface
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-001/00
G06F-001/04
G06F-001/32
출원번호
US-0190645
(2011-07-26)
등록번호
US-8850248
(2014-09-30)
우선권정보
TW-100114162 A (2011-04-22)
발명자
/ 주소
Hou, Ping-Cheng
Lu, Cheng-Yu
Shih, Chieh-Wen
Wu, Jen-Shi
Chen, Chung-Ching
출원인 / 주소
MStar Semiconductor, Inc.
대리인 / 주소
Edell, Shapiro & Finnan, LLC
인용정보
피인용 횟수 :
0인용 특허 :
6
초록▼
A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmissio
A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmission interface. The rate adjustment module receives the bandwidth requirements, and determines a transmission rate of the data transmission interface according to the bandwidth requirements.
대표청구항▼
1. A multi-core electronic system, configured to access a data storage device, the multi-core electronic system comprising: a plurality of processors each configured to provide a bandwidth requirement, wherein each bandwidth requirement is associated with a bandwidth value;a shared data transmission
1. A multi-core electronic system, configured to access a data storage device, the multi-core electronic system comprising: a plurality of processors each configured to provide a bandwidth requirement, wherein each bandwidth requirement is associated with a bandwidth value;a shared data transmission interface, via which the processors are configured to communicate with the data storage device, wherein the shared data transmission interface supports multiple transmission rates, each associated with one of a plurality of intervals of transmission rates; anda rate adjustment module, configured to receive the bandwidth requirements, generate a total bandwidth requirement from addition of the bandwidth values of the bandwidth requirements, select a minimum transmission rate that is capable of meeting the total bandwidth requirement, and provide the minimum transmission rate to the shared data transmission interface,wherein the rate adjustment module is further configured to select a group of settings associated with the minimum transmission rate from predetermined reference information according to the interval into which the minimum transmission rate falls. 2. The multi-core electronic system according to claim 1, wherein the rate adjustment module is configured to periodically check whether the minimum transmission rate needs to be adjusted. 3. The multi-core electronic system according to claim 1, wherein the bandwidth requirement comprises an imminence index, and the rate adjustment module is configured to determine when to adjust the minimum transmission rate according to the imminence index. 4. The multi-core electronic system according to claim 1, wherein the rate adjustment module is independent from the processors and is dedicated for determining the minimum transmission rate according to the bandwidth requirements. 5. The multi-core electronic system according to claim 1, wherein the adjustment module is realized by a software program executed by one of the processors. 6. The multi-core electronic system according to claim 1, wherein the data storage device comprises a memory built in the multi-core electronic system or a pluggable memory applicable to the multi-core electronic system. 7. The multi-core electronic system according to claim 1, wherein the rate adjustment module comprises a finite state machine configured to control changes to the minimum transmission rate. 8. A rate adjustment device, applicable to a multi-core electronic system, the multi-core electronic system comprising a plurality of processors and communicating with a data storage device via a shared data transmission interface, the rate adjustment device comprising: a receiving unit, configured to receive a plurality of bandwidth requirements respectively provided by the processors, wherein each bandwidth requirement associates with a bandwidth value; anda rate adjustment unit, configured to generate a total bandwidth requirement from addition of the bandwidth values of the bandwidth requirements, select a minimum transmission rate capable of meeting the total bandwidth requirement, and provide the minimum transmission rate to the shared data transmission interface,wherein the shared data transmission interface supports multiple transmission rates, each associated with one of a plurality of intervals of transmission rates, andwherein the rate adjustment unit is configured to select, from predetermined reference information, a group of settings associated with the minimum transmission rate according to the interval into which the minimum transmission rate falls. 9. The rate adjustment device according to claim 8, wherein the rate adjustment unit is configured to periodically check whether the minimum transmission rate needs to be adjusted. 10. The rate adjustment device according to claim 8, wherein the bandwidth requirement comprises an imminence index, and the rate adjustment unit is configured to determine when to adjust the minimum transmission rate according to the imminence index. 11. The rate adjustment device according to claim 8, further comprising a finite state machine configured to control changes to the minimum transmission rate.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (6)
Li, Wenlong; Tong, Xiaofeng; Jaleel, Aamer, Device, system, and method of scheduling tasks of a multithreaded application.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.