최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0242308 (2014-04-01) |
등록번호 | US-8853794 (2014-10-07) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 9 인용 특허 : 514 |
A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electr
A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and a conductive interconnect structure.
1. An integrated circuit within a semiconductor chip, comprising: a first transistor of a first transistor type having a gate electrode, a first diffusion terminal of a first diffusion type, and a second diffusion terminal of the first diffusion type;a second transistor of the first transistor type
1. An integrated circuit within a semiconductor chip, comprising: a first transistor of a first transistor type having a gate electrode, a first diffusion terminal of a first diffusion type, and a second diffusion terminal of the first diffusion type;a second transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;a third transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;a fourth transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;a first transistor of a second transistor type having a gate electrode, a first diffusion terminal of a second diffusion type, and a second diffusion terminal of the second diffusion type;a second transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type;a third transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type;a fourth transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type,both the gate electrode of the first transistor of the first transistor type and the gate electrode of the first transistor of the second transistor type formed by a first linear-shaped conductive structure, the gate electrode of the first transistor of the first transistor type electrically connected to the gate electrode of the first transistor of the second transistor type through the first linear-shaped conductive structure,the gate electrode of the second transistor of the first transistor type formed by a second linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the second linear-shaped conductive structure is of the first transistor type,the gate electrode of the second transistor of the second transistor type formed by a third linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the third linear-shaped conductive structure is of the second transistor type,the first, second, and third linear-shaped conductive structures oriented to extend lengthwise in a first direction,the first linear-shaped conductive structure positioned between the second and third linear-shaped conductive structures in a second direction perpendicular to the first direction,the first, second, third, and fourth transistors of the first transistor type forming a first collection of transistors,the first, second, third, and fourth transistors of the second transistor type forming a second collection of transistors,the first collection of transistors separated from the second collection of transistors by an inner region that does not include a source or a drain of any transistor,the first and second transistors of the first transistor type positioned adjacent to each other, the first diffusion terminal of the first transistor of the first transistor type electrically and physically connected to the first diffusion terminal of the second transistor of the first transistor type, the first diffusion terminal of the first transistor of the first transistor type also electrically connected to a common node, the first diffusion terminal of the second transistor of the first transistor type also electrically connected to the common node,the first and second transistors of the second transistor type positioned adjacent to each other, the first diffusion terminal of the first transistor of the second transistor type electrically and physically connected to the first diffusion terminal of the second transistor of the second transistor type, the first diffusion terminal of the first transistor of the second transistor type also electrically connected to the common node, the first diffusion terminal of the second transistor of the second transistor type also electrically connected to the common node,the first diffusion terminal of the third transistor of the first transistor type electrically connected to the second diffusion terminal of the first transistor of the first transistor type,the first diffusion terminal of the fourth transistor of the first transistor type electrically connected to the second diffusion terminal of the second transistor of the first transistor type,the first diffusion terminal of the third transistor of the second transistor type electrically connected to the second diffusion terminal of the first transistor of the second transistor type,the first diffusion terminal of the fourth transistor of the second transistor type electrically connected to the second diffusion terminal of the second transistor of the second transistor type,the gate electrode of the third transistor of the first transistor type electrically connected to the gate electrode of the fourth transistor of the second transistor type,the gate electrode of the third transistor of the second transistor type electrically connected to the gate electrode of the fourth transistor of the first transistor type;a first interconnect conductive structure located within a first interconnect chip level of the semiconductor chip, the first interconnect chip level formed above a level of the semiconductor chip that includes the first, second, and third linear-shaped conductive structures;a second interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the second interconnect conductive structure physically separate from the first interconnect conductive structure;a first gate contact in contact with the first linear-shaped conductive structure, the first gate contact formed to extend in a vertical direction substantially perpendicular to a substrate of the semiconductor chip from the first linear-shaped conductive structure through a dielectric material to contact the second interconnect conductive structure;a second gate contact in contact with the second linear-shaped conductive structure, the second gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the second linear-shaped conductive structure through the dielectric material to contact the first interconnect conductive structure;a third gate contact in contact with the third linear-shaped conductive structure, the third gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the third linear-shaped conductive structure through the dielectric material to contact the first interconnect conductive structure,wherein the first interconnect conductive structure is physically separate from the first gate contact, and wherein the second interconnect conductive structure is physically separate from the second and third gate contacts,the integrated circuit being part of a digital logic circuit. 2. The integrated circuit within the semiconductor chip as recited in claim 1, wherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type by a first pitch, the first pitch being a distance measured in the second direction perpendicular to the first direction, and wherein the lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the first transistor type by the first pitch, andwherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type by the first pitch, andwherein a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the second transistor type by the first pitch, andwherein the first diffusion terminal of the fourth transistor of the first transistor type is physically connected to the second diffusion terminal of the second transistor of the first transistor type, andwherein the first diffusion terminal of the fourth transistor of the second transistor type is physically connected to the second diffusion terminal of the second transistor of the second transistor type, andwherein the gate electrode of the third transistor of the first transistor type is formed as part of a fourth linear-shaped conductive structure, and wherein the gate electrode of the fourth transistor of the second transistor type is also formed as part of the fourth linear-shaped conductive structure, andwherein the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the first transistor type by a second pitch, the second pitch being a distance measured in the second direction perpendicular to the first direction, the second pitch substantially equal to two times the first pitch, andwherein the gate electrode of the fourth transistor of the first transistor type is formed as part of a fifth linear-shaped conductive structure, and wherein the gate electrode of the third transistor of the second transistor type is also formed as part of the fifth linear-shaped conductive structure, andwherein the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the second transistor type by the second pitch, andwherein a size of the first linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the second linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the third linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the fourth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the fifth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers. 3. The integrated circuit within the semiconductor chip as recited in claim 2, wherein either a) the first diffusion terminal of the third transistor of the first transistor type is electrically connected to the second diffusion terminal of the first transistor of the first transistor type through at least one conductive structure formed in a level of the semiconductor chip above a diffusion level of the semiconductor chip, orb) the first diffusion terminal of the third transistor of the second transistor type is electrically connected to the second diffusion terminal of the first transistor of the second transistor type through at least one conductive structure formed in a level of the semiconductor chip above a diffusion level of the semiconductor chip, orboth a) and b). 4. The integrated circuit within the semiconductor chip as recited in claim 3, further comprising: a sixth linear-shaped conductive structure that does not form a gate electrode of any transistor,the sixth linear-shaped conductive structure positioned in a side-by-side manner with multiple adjacently positioned linear-shaped conductive structures that collectively form gate electrodes of two adjacently positioned transistors of the first transistor type and gate electrodes of two adjacently positioned transistors of the second transistor type,at least one of the multiple adjacently positioned linear-shaped conductive structures being a multiple gate electrode forming linear-shaped conductive structure that forms both a gate electrode of one of the two adjacently positioned transistors of the first transistor type and a gate electrode of one of the two adjacently positioned transistors of the second transistor type,the sixth linear-shaped conductive structure and each of the multiple adjacently positioned linear-shaped conductive structures having a corresponding lengthwise centerline oriented in the first direction,the sixth linear-shaped conductive structure having a total length as measured in the first direction at least equal to a total length of the multiple gate electrode forming linear-shaped conductive structure as measured in the first direction,the lengthwise centerline of the sixth linear-shaped conductive structure separated from each lengthwise centerline of each of the multiple adjacently positioned linear-shaped conductive structures by a distance as measured in the second direction substantially equal to the first pitch,the sixth linear-shaped conductive structure defined to extend lengthwise from a first end to a second end,the first end of the sixth linear-shaped conductive structure substantially aligned with an end of at least one of the multiple adjacently positioned linear-shaped conductive structures that forms the gate electrode of one of the two adjacently positioned transistors of the first transistor type,the second end of the sixth linear-shaped conductive structure substantially aligned with an end of at least one of the multiple adjacently positioned linear-shaped conductive structures that forms the gate electrode of one of the two adjacently positioned transistors of the second transistor type. 5. The integrated circuit within the semiconductor chip as recited in claim 4, wherein the common node includes a number of conductive structures that include at least one interconnect conductive structure within the first interconnect chip level of the semiconductor chip. 6. The integrated circuit within the semiconductor chip as recited in claim 5, wherein the first gate contact is the only gate contact in physical contact with the first linear-shaped conductive structure, and wherein the second gate contact is the only gate contact in physical contact with the second linear-shaped conductive structure, and wherein the third gate contact is the only gate contact in physical contact with the third linear-shaped conductive structure, wherein the first gate contact extends over a first distance as measured in the first direction, a midpoint of the first distance corresponding to a first direction midpoint of the first gate contact, the first gate contact having a second direction oriented centerline extending in the second direction through the first direction midpoint of the first gate contact,wherein the second gate contact extends over a second distance as measured in the first direction, a midpoint of the second distance corresponding to a first direction midpoint of the second gate contact, the second gate contact having a second direction oriented centerline extending in the second direction through the first direction midpoint of the second gate contact,wherein the third gate contact extends over a third distance as measured in the first direction, a midpoint of the third distance corresponding to a first direction midpoint of the third gate contact, the third gate contact having a second direction oriented centerline extending in the second direction through the first direction midpoint of the third gate contact, andwherein the second direction oriented centerline of the second gate contact is substantially aligned with the second direction oriented centerline of the third gate contact. 7. The integrated circuit within the semiconductor chip as recited in claim 6, wherein a total length of the first linear-shaped conductive structure as measured in the first direction is substantially equal to a total length of the second linear-shaped conductive structure as measured in the first direction. 8. The integrated circuit within the semiconductor chip as recited in claim 7, wherein the integrated circuit includes electrical connections formed by one or more of multiple interconnect conductive structures within one or more of a number of interconnect chip levels, the number of interconnect chip levels including the first interconnect chip level and any interconnect chip level above the first interconnect chip level, each of the multiple interconnect conductive structures forming any electrical connection within the integrated circuit having a linear-shape. 9. The integrated circuit within the semiconductor chip as recited in claim 4, further comprising: a third interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the third interconnect conductive structure physically separate from the first and second interconnect conductive structures;a fourth interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the fourth interconnect conductive structure physically separate from the first, second, and third interconnect conductive structures;a fourth gate contact in contact with the fourth linear-shaped conductive structure, the fourth gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the fourth linear-shaped conductive structure through the dielectric material to contact the third interconnect conductive structure; anda fifth gate contact in contact with the fifth linear-shaped conductive structure, the fifth gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the fifth linear-shaped conductive structure through the dielectric material to contact the fourth interconnect conductive structure,wherein the third interconnect conductive structure is physically separate from the first, second, third, and fifth gate contacts,wherein the fourth interconnect conductive structure is physically separate from the first, second, third, and fourth gate contacts,wherein the integrated circuit is included within a single layout cell. 10. The integrated circuit within the semiconductor chip as recited in claim 9, wherein a total length of the first linear-shaped conductive structure as measured in the first direction is substantially equal to a total length of the second linear-shaped conductive structure as measured in the first direction. 11. The integrated circuit within the semiconductor chip as recited in claim 4, wherein a size of the first linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 34 nanometers, and wherein a size of the second linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 34 nanometers, andwherein a size of the third linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 34 nanometers, andwherein a size of the fourth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 34 nanometers, andwherein a size of the fifth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 34 nanometers. 12. The integrated circuit within the semiconductor chip as recited in claim 1, further comprising: a fourth linear-shaped conductive structure oriented to extend lengthwise in the first direction;a fifth linear-shaped conductive structure oriented to extend lengthwise in the first direction;a third interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the third interconnect conductive structure physically separate from the first and second interconnect conductive structures;a fourth interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the fourth interconnect conductive structure physically separate from the first, second, and third interconnect conductive structures;a fourth gate contact in contact with the fourth linear-shaped conductive structure, the fourth gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the fourth linear-shaped conductive structure through the dielectric material to contact the third interconnect conductive structure; anda fifth gate contact in contact with the fifth linear-shaped conductive structure, the fifth gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the fifth linear-shaped conductive structure through the dielectric material to contact the fourth interconnect conductive structure,wherein the third interconnect conductive structure is physically separate from the first, second, third, and fifth gate contacts,wherein the fourth interconnect conductive structure is physically separate from the first, second, third, and fourth gate contacts,wherein the gate electrode of the third transistor of the first transistor type is formed as part of the fourth linear-shaped conductive structure,wherein the gate electrode of the fourth transistor of the second transistor type is also formed as part of the fourth linear-shaped conductive structure,wherein the gate electrode of the fourth transistor of the first transistor type is formed as part of the fifth linear-shaped conductive structure,wherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type by a pitch, the pitch being a distance measured in the second direction perpendicular to the first direction,wherein a corresponding distance as measured in the second direction between any two lengthwise centerlines of the first, second, third, fourth, and fifth linear-shaped conductive structures is substantially equal to a corresponding integer multiple of the pitch,wherein a size of the first linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the second linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the third linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the fourth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the fifth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers. 13. The integrated circuit within the semiconductor chip as recited in claim 12, further comprising: a sixth linear-shaped conductive structure that does not form a gate electrode of any transistor,the sixth linear-shaped conductive structure positioned in a side-by-side manner with multiple adjacently positioned linear-shaped conductive structures that collectively form gate electrodes of two adjacently positioned transistors of the first transistor type and gate electrodes of two adjacently positioned transistors of the second transistor type,at least one of the multiple adjacently positioned linear-shaped conductive structures being a multiple gate electrode forming linear-shaped conductive structure that forms both a gate electrode of one of the two adjacently positioned transistors of the first transistor type and a gate electrode of one of the two adjacently positioned transistors of the second transistor type,the sixth linear-shaped conductive structure and each of the multiple adjacently positioned linear-shaped conductive structures having a corresponding lengthwise centerline oriented in the first direction,the sixth linear-shaped conductive structure having a total length as measured in the first direction at least equal to a total length of the multiple gate electrode forming linear-shaped conductive structure as measured in the first direction,the lengthwise centerline of the sixth linear-shaped conductive structure separated from each lengthwise centerline of each of the multiple adjacently positioned linear-shaped conductive structures by a distance as measured in the second direction substantially equal to the pitch,the sixth linear-shaped conductive structure defined to extend lengthwise from a first end to a second end,the first end of the sixth linear-shaped conductive structure substantially aligned with an end of at least one of the multiple adjacently positioned linear-shaped conductive structures that forms the gate electrode of one of the two adjacently positioned transistors of the first transistor type,the second end of the sixth linear-shaped conductive structure substantially aligned with an end of at least one of the multiple adjacently positioned linear-shaped conductive structures that forms the gate electrode of one of the two adjacently positioned transistors of the second transistor type. 14. The integrated circuit within the semiconductor chip as recited in claim 13, wherein the integrated circuit includes electrical connections formed by one or more of multiple interconnect conductive structures within one or more of a number of interconnect chip levels, the number of interconnect chip levels including the first interconnect chip level and any interconnect chip level above the first interconnect chip level, each of the multiple interconnect conductive structures forming any electrical connection within the integrated circuit having a linear-shape. 15. The integrated circuit within the semiconductor chip as recited in claim 1, wherein the integrated circuit includes at least one linear-shaped conductive structure of a first extension type defined to form at least one gate electrode of at least one transistor of the first transistor type, wherein any transistor having its gate electrode formed by the at least one linear-shaped conductive structure of the first extension type is of the first transistor type, wherein the at least one linear-shaped conductive structure of the first extension type extends lengthwise in the first direction through the inner region and completely past a diffusion terminal of at least one transistor of the second transistor type, and wherein the integrated circuit includes at least one linear-shaped conductive structure of a second extension type defined to form at least one gate electrode of at least one transistor of the second transistor type, wherein any transistor having its gate electrode formed by the at least one linear-shaped conductive structure of the second extension type is of the second transistor type, wherein the at least one linear-shaped conductive structure of the second extension type extends lengthwise in the first direction through the inner region and completely past a diffusion terminal of at least one transistor of the first transistor type. 16. The integrated circuit within the semiconductor chip as recited in claim 15, wherein the at least one linear-shaped conductive structure of the first extension type is the second linear-shaped conductive structure, or wherein the at least one linear-shaped conductive structure of the second extension type is the third linear-shaped conductive structure. 17. The integrated circuit within the semiconductor chip as recited in claim 16, wherein the at least one linear-shaped conductive structure of the first extension type extends lengthwise in the first direction between at least two diffusion terminals of the second diffusion type, or wherein the at least one linear-shaped conductive structure of the second extension type extends lengthwise in the first direction between at least two diffusion terminals of the first diffusion type. 18. The integrated circuit within the semiconductor chip as recited in claim 17, wherein the at least one linear-shaped conductive structure of the first extension type is the second linear-shaped conductive structure and the at least one linear-shaped conductive structure of the second extension type is the third linear-shaped conductive structure, and wherein the second linear-shaped conductive structure extends lengthwise in the first direction between at least two diffusion terminals of the second diffusion type, andwherein the third linear-shaped conductive structure extends lengthwise in the first direction between at least two diffusion terminals of the first diffusion type. 19. The integrated circuit within the semiconductor chip as recited in claim 18, wherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type by a first pitch, the first pitch being a distance measured in the second direction perpendicular to the first direction, and wherein the lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the first transistor type by the first pitch, andwherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type by the first pitch, andwherein a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the second transistor type by the first pitch, andwherein the first diffusion terminal of the fourth transistor of the first transistor type and the second diffusion terminal of the second transistor of the first transistor type are a same diffusion terminal of the first diffusion type, andwherein the first diffusion terminal of the fourth transistor of the second transistor type and the second diffusion terminal of the second transistor of the second transistor type are a same diffusion terminal of the second diffusion type, andwherein the gate electrode of the third transistor of the first transistor type is formed as part of a fourth linear-shaped conductive structure, and wherein the gate electrode of the fourth transistor of the second transistor type is also formed as part of the fourth linear-shaped conductive structure, andwherein the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the first transistor type by a second pitch, the second pitch being a distance measured in the second direction perpendicular to the first direction, the second pitch substantially equal to two times the first pitch, andwherein the gate electrode of the fourth transistor of the first transistor type is formed as part of a fifth linear-shaped conductive structure, and wherein the gate electrode of the third transistor of the second transistor type is also formed as part of the fifth linear-shaped conductive structure, andwherein the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the second transistor type by the second pitch, andwherein a size of the first linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the second linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the third linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the fourth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the fifth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers. 20. The integrated circuit within the semiconductor chip as recited in claim 19, wherein the first gate contact is the only gate contact in physical contact with the first linear-shaped conductive structure, and wherein the second gate contact is the only gate contact in physical contact with the second linear-shaped conductive structure, and wherein the third gate contact is the only gate contact in physical contact with the third linear-shaped conductive structure, wherein the first gate contact extends over a first distance as measured in the first direction, a midpoint of the first distance corresponding to a first direction midpoint of the first gate contact, the first gate contact having a second direction oriented centerline extending in the second direction through the first direction midpoint of the first gate contact,wherein the second gate contact extends over a second distance as measured in the first direction, a midpoint of the second distance corresponding to a first direction midpoint of the second gate contact, the second gate contact having a second direction oriented centerline extending in the second direction through the first direction midpoint of the second gate contact,wherein the third gate contact extends over a third distance as measured in the first direction, a midpoint of the third distance corresponding to a first direction midpoint of the third gate contact, the third gate contact having a second direction oriented centerline extending in the second direction through the first direction midpoint of the third gate contact,wherein the second direction oriented centerline of the second gate contact is substantially aligned with the second direction oriented centerline of the third gate contact. 21. The integrated circuit within the semiconductor chip as recited in claim 16, wherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type by a first pitch, the first pitch being a distance measured in the second direction perpendicular to the first direction, and wherein the lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the first transistor type by the first pitch, andwherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type by the first pitch, andwherein a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the second transistor type by the first pitch, andwherein the first diffusion terminal of the fourth transistor of the first transistor type and the second diffusion terminal of the second transistor of the first transistor type are a same diffusion terminal of the first diffusion type, andwherein the first diffusion terminal of the fourth transistor of the second transistor type and the second diffusion terminal of the second transistor of the second transistor type are a same diffusion terminal of the second diffusion type, andwherein the gate electrode of the third transistor of the first transistor type is formed as part of a fourth linear-shaped conductive structure, and wherein the gate electrode of the fourth transistor of the second transistor type is also formed as part of the fourth linear-shaped conductive structure, andwherein the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the first transistor type by a second pitch, the second pitch being a distance measured in the second direction perpendicular to the first direction, the second pitch substantially equal to two times the first pitch, andwherein the gate electrode of the fourth transistor of the first transistor type is formed as part of a fifth linear-shaped conductive structure, and wherein the gate electrode of the third transistor of the second transistor type is also formed as part of the fifth linear-shaped conductive structure, andwherein the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the second transistor type by the second pitch, andwherein a size of the first linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the second linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the third linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the fourth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers, andwherein a size of the fifth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers. 22. The integrated circuit within the semiconductor chip as recited in claim 21, wherein the common node includes a number of conductive structures that include at least one interconnect conductive structure within the first interconnect chip level of the semiconductor chip. 23. The integrated circuit within the semiconductor chip as recited in claim 22, wherein the first gate contact is the only gate contact in physical contact with the first linear-shaped conductive structure, and wherein the second gate contact is the only gate contact in physical contact with the second linear-shaped conductive structure, and wherein the third gate contact is the only gate contact in physical contact with the third linear-shaped conductive structure, wherein the first gate contact extends over a first distance as measured in the first direction, a midpoint of the first distance corresponding to a first direction midpoint of the first gate contact, the first gate contact having a second direction oriented centerline extending in the second direction through the first direction midpoint of the first gate contact,wherein the second gate contact extends over a second distance as measured in the first direction, a midpoint of the second distance corresponding to a first direction midpoint of the second gate contact, the second gate contact having a second direction oriented centerline extending in the second direction through the first direction midpoint of the second gate contact,wherein the third gate contact extends over a third distance as measured in the first direction, a midpoint of the third distance corresponding to a first direction midpoint of the third gate contact, the third gate contact having a second direction oriented centerline extending in the second direction through the first direction midpoint of the third gate contactwherein the second direction oriented centerline of the second gate contact is substantially aligned with the second direction oriented centerline of the third gate contact. 24. The integrated circuit within the semiconductor chip as recited in claim 23, further comprising: a sixth linear-shaped conductive structure that does not form a gate electrode of any transistor,the sixth linear-shaped conductive structure positioned in a side-by-side manner with multiple adjacently positioned linear-shaped conductive structures that collectively form gate electrodes of two adjacently positioned transistors of the first transistor type and gate electrodes of two adjacently positioned transistors of the second transistor type,at least one of the multiple adjacently positioned linear-shaped conductive structures being a multiple gate electrode forming linear-shaped conductive structure that forms both a gate electrode of one of the two adjacently positioned transistors of the first transistor type and a gate electrode of one of the two adjacently positioned transistors of the second transistor type,the sixth linear-shaped conductive structure and each of the multiple adjacently positioned linear-shaped conductive structures having a corresponding lengthwise centerline oriented in the first direction,the sixth linear-shaped conductive structure having a total length as measured in the first direction at least equal to a total length of the multiple gate electrode forming linear-shaped conductive structure as measured in the first direction,the lengthwise centerline of the sixth linear-shaped conductive structure separated from each lengthwise centerline of each of the multiple adjacently positioned linear-shaped conductive structures by a distance as measured in the second direction substantially equal to the first pitch,the sixth linear-shaped conductive structure defined to extend lengthwise from a first end to a second end,the first end of the sixth linear-shaped conductive structure substantially aligned with an end of at least one of the multiple adjacently positioned linear-shaped conductive structures that forms the gate electrode of one of the two adjacently positioned transistors of the first transistor type,the second end of the sixth linear-shaped conductive structure substantially aligned with an end of at least one of the multiple adjacently positioned linear-shaped conductive structures that forms the gate electrode of one of the two adjacently positioned transistors of the second transistor type. 25. The integrated circuit within the semiconductor chip as recited in claim 24, wherein the integrated circuit includes electrical connections formed by one or more of multiple interconnect conductive structures within one or more of a number of interconnect chip levels, the number of interconnect chip levels including the first interconnect chip level and any interconnect chip level above the first interconnect chip level, each of the multiple interconnect conductive structures forming any electrical connection within the integrated circuit having a linear-shape. 26. The integrated circuit within the semiconductor chip as recited in claim 24, wherein the integrated circuit is included within a single layout cell. 27. A method for creating a layout of an integrated circuit for a semiconductor chip, comprising: operating a computer to define a first transistor of a first transistor type having a gate electrode, a first diffusion terminal of a first diffusion type, and a second diffusion terminal of the first diffusion type;operating the computer to define a second transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;operating the computer to define a third transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;operating the computer to define a fourth transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;operating the computer to define a first transistor of a second transistor type having a gate electrode, a first diffusion terminal of a second diffusion type, and a second diffusion terminal of the second diffusion type;operating the computer to define a second transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type;operating the computer to define a third transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type;operating the computer to define a fourth transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type,both the gate electrode of the first transistor of the first transistor type and the gate electrode of the first transistor of the second transistor type formed by a layout feature corresponding to a first linear-shaped conductive structure such that the gate electrode of the first transistor of the first transistor type electrically connects to the gate electrode of the first transistor of the second transistor type through the first linear-shaped conductive structure,the gate electrode of the second transistor of the first transistor type formed by a layout feature corresponding to a second linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the second linear-shaped conductive structure is of the first transistor type,the gate electrode of the second transistor of the second transistor type formed by a layout feature corresponding to a third linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the third linear-shaped conductive structure is of the second transistor type,the gate electrode of the third transistor of the first transistor type formed by a layout feature corresponding to a fourth linear-shaped conductive structure,the gate electrode of the fourth transistor of the second transistor type also formed as part of the layout feature corresponding to the fourth linear-shaped conductive structure,the gate electrode of the fourth transistor of the first transistor type formed by a layout feature corresponding to a fifth linear-shaped conductive structure,the gate electrode of the third transistor of the second transistor type also formed as part of the layout feature corresponding to the fifth linear-shaped conductive structure,the layout features respectively corresponding to the first, second, third, fourth, and fifth linear-shaped conductive structures oriented to extend lengthwise in a first direction,the layout feature corresponding to the first linear-shaped conductive structure positioned between the layout features respectively corresponding to the second and third linear-shaped conductive structures in a second direction perpendicular to the first direction,the first, second, third, and fourth transistors of the first transistor type forming a first collection of transistors,the first, second, third, and fourth transistors of the second transistor type forming a second collection of transistors,the first collection of transistors separated from the second collection of transistors by an inner region that does not include a source or a drain of any transistor,the first and second transistors of the first transistor type positioned adjacent to each other such that the first diffusion terminal of the first transistor of the first transistor type electrically and physically connects to the first diffusion terminal of the second transistor of the first transistor type, and such that the first diffusion terminal of the first transistor of the first transistor type electrically connects to a common node, and such that the first diffusion terminal of the second transistor of the first transistor type electrically connects to the common node,the first and second transistors of the second transistor type positioned adjacent to each other such that the first diffusion terminal of the first transistor of the second transistor type electrically and physically connects to the first diffusion terminal of the second transistor of the second transistor type, and such that the first diffusion terminal of the first transistor of the second transistor type electrically connects to the common node, and such that the first diffusion terminal of the second transistor of the second transistor type electrically connects to the common node,the fourth and second transistors of the first transistor type positioned adjacent to each other such that the first diffusion terminal of the fourth transistor of the first transistor type electrically and physically connects to the second diffusion terminal of the second transistor of the first transistor type,the fourth and second transistors of the second transistor type positioned adjacent to each other such that the first diffusion terminal of the fourth transistor of the second transistor type electrically and physically connects to the second diffusion terminal of the second transistor of the second transistor type,wherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type by a first pitch, the first pitch being a distance measured in the second direction perpendicular to the first direction,wherein the lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the first transistor type by the first pitch,wherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type by the first pitch,wherein a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the second transistor type by the first pitch,wherein the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the first transistor type by a second pitch, the second pitch being a distance measured in the second direction perpendicular to the first direction, the second pitch substantially equal to two times the first pitch,wherein the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the second transistor type by the second pitch,wherein a size of the first linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the second linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the third linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the fourth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the fifth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers;operating the computer to define one or more layout features to electrically connect the first diffusion terminal of the third transistor of the first transistor type to the second diffusion terminal of the first transistor of the first transistor type;operating the computer to define one or more layout features to electrically connect the first diffusion terminal of the fourth transistor of the first transistor type to the second diffusion terminal of the second transistor of the first transistor type;operating the computer to define one or more layout features to electrically connect the first diffusion terminal of the third transistor of the second transistor type to the second diffusion terminal of the first transistor of the second transistor type;operating the computer to define one or more layout features to electrically connect the first diffusion terminal of the fourth transistor of the second transistor type to the second diffusion terminal of the second transistor of the second transistor type;operating the computer to define one or more layout features to electrically connect the gate electrode of the third transistor of the first transistor type to the gate electrode of the fourth transistor of the second transistor type;operating the computer to define one or more layout features to electrically connect the gate electrode of the third transistor of the second transistor type to the gate electrode of the fourth transistor of the first transistor type;operating the computer to define a layout feature of a first interconnect conductive structure located within a first interconnect chip level of the semiconductor chip, the first interconnect chip level formed above a level of the semiconductor chip that includes the first, second, third, fourth, and fifth linear-shaped conductive structures;operating the computer to define a layout feature of a second interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the second interconnect conductive structure defined to be physically separate from the first interconnect conductive structure;operating the computer to define a layout feature of a third interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the third interconnect conductive structure defined to be physically separate from the first and second interconnect conductive structures;operating the computer to define a layout feature of a fourth interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the fourth interconnect conductive structure defined to be physically separate from the first, second, and third interconnect conductive structures;operating the computer to define a layout feature of a first gate contact to contact the first linear-shaped conductive structure, the first gate contact defined to extend in a vertical direction substantially perpendicular to a substrate of the semiconductor chip from the first linear-shaped conductive structure through a dielectric material to contact the second interconnect conductive structure;operating the computer to define a layout feature of a second gate contact to contact the second linear-shaped conductive structure, the second gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the second linear-shaped conductive structure through the dielectric material to contact the first interconnect conductive structure;operating the computer to define a layout feature of a third gate contact to contact the third linear-shaped conductive structure, the third gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the third linear-shaped conductive structure through the dielectric material to contact the first interconnect conductive structure;operating the computer to define a layout feature of a fourth gate contact to contact the fourth linear-shaped conductive structure, the fourth gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the fourth linear-shaped conductive structure through the dielectric material to contact the third interconnect conductive structure;operating the computer to define a layout feature of a fifth gate contact to contact the fifth linear-shaped conductive structure, the fifth gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the fifth linear-shaped conductive structure through the dielectric material to contact the fourth interconnect conductive structure,wherein the first interconnect conductive structure is defined to be physically separate from the first, fourth, and fifth gate contacts, andwherein the second interconnect conductive structure is defined to be physically separate from the second, third, fourth, and fifth gate contacts, andwherein the third interconnect conductive structure is defined to be physically separate from the first, second, third, and fifth gate contacts, andwherein the fourth interconnect conductive structure is defined to be physically separate from the first, second, third, and fourth gate contacts,the integrated circuit being part of a digital logic circuit. 28. A data storage device having program instructions stored thereon for generating a layout of an integrated circuit for a semiconductor chip, comprising: program instructions for defining a first transistor of a first transistor type having a gate electrode, a first diffusion terminal of a first diffusion type, and a second diffusion terminal of the first diffusion type;program instructions for defining a second transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;program instructions for defining a third transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;program instructions for defining a fourth transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;program instructions for defining a first transistor of a second transistor type having a gate electrode, a first diffusion terminal of a second diffusion type, and a second diffusion terminal of the second diffusion type;program instructions for defining a second transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type;program instructions for defining a third transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type;program instructions for defining a fourth transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type,both the gate electrode of the first transistor of the first transistor type and the gate electrode of the first transistor of the second transistor type formed by a layout feature corresponding to a first linear-shaped conductive structure such that the gate electrode of the first transistor of the first transistor type electrically connects to the gate electrode of the first transistor of the second transistor type through the first linear-shaped conductive structure,the gate electrode of the second transistor of the first transistor type formed by a layout feature corresponding to a second linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the second linear-shaped conductive structure is of the first transistor type,the gate electrode of the second transistor of the second transistor type formed by a layout feature corresponding to a third linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the third linear-shaped conductive structure is of the second transistor type,the gate electrode of the third transistor of the first transistor type formed by a layout feature corresponding to a fourth linear-shaped conductive structure,the gate electrode of the fourth transistor of the second transistor type also formed as part of the layout feature corresponding to the fourth linear-shaped conductive structure,the gate electrode of the fourth transistor of the first transistor type formed by a layout feature corresponding to a fifth linear-shaped conductive structure,the gate electrode of the third transistor of the second transistor type also formed as part of the layout feature corresponding to the fifth linear-shaped conductive structure,the layout features respectively corresponding to the first, second, third, fourth, and fifth linear-shaped conductive structures oriented to extend lengthwise in a first direction,the layout feature corresponding to the first linear-shaped conductive structure positioned between the layout features respectively corresponding to the second and third linear-shaped conductive structures in a second direction perpendicular to the first direction,the first, second, third, and fourth transistors of the first transistor type forming a first collection of transistors,the first, second, third, and fourth transistors of the second transistor type forming a second collection of transistors,the first collection of transistors separated from the second collection of transistors by an inner region that does not include a source or a drain of any transistor,the first and second transistors of the first transistor type positioned adjacent to each other such that the first diffusion terminal of the first transistor of the first transistor type electrically and physically connects to the first diffusion terminal of the second transistor of the first transistor type, and such that the first diffusion terminal of the first transistor of the first transistor type electrically connects to a common node, and such that the first diffusion terminal of the second transistor of the first transistor type electrically connects to the common node,the first and second transistors of the second transistor type positioned adjacent to each other such that the first diffusion terminal of the first transistor of the second transistor type electrically and physically connects to the first diffusion terminal of the second transistor of the second transistor type, and such that the first diffusion terminal of the first transistor of the second transistor type electrically connects to the common node, and such that the first diffusion terminal of the second transistor of the second transistor type electrically connects to the common node,the fourth and second transistors of the first transistor type positioned adjacent to each other such that the first diffusion terminal of the fourth transistor of the first transistor type electrically and physically connects to the second diffusion terminal of the second transistor of the first transistor type,the fourth and second transistors of the second transistor type positioned adjacent to each other such that the first diffusion terminal of the fourth transistor of the second transistor type electrically and physically connects to the second diffusion terminal of the second transistor of the second transistor type,wherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type by a first pitch, the first pitch being a distance measured in the second direction perpendicular to the first direction,wherein the lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the first transistor type by the first pitch,wherein a lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type by the first pitch,wherein a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the second transistor type by the first pitch,wherein the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the first transistor type by a second pitch, the second pitch being a distance measured in the second direction perpendicular to the first direction, the second pitch substantially equal to two times the first pitch,wherein the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type is separated from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the second transistor type by the second pitch,wherein a size of the first linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the second linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the third linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the fourth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers,wherein a size of the fifth linear-shaped conductive structure as measured in the second direction perpendicular to the first direction is less than 193 nanometers;program instructions for defining one or more layout features to electrically connect the first diffusion terminal of the third transistor of the first transistor type to the second diffusion terminal of the first transistor of the first transistor type;program instructions for defining one or more layout features to electrically connect the first diffusion terminal of the fourth transistor of the first transistor type to the second diffusion terminal of the second transistor of the first transistor type;program instructions for defining one or more layout features to electrically connect the first diffusion terminal of the third transistor of the second transistor type to the second diffusion terminal of the first transistor of the second transistor type;program instructions for defining one or more layout features to electrically connect the first diffusion terminal of the fourth transistor of the second transistor type to the second diffusion terminal of the second transistor of the second transistor type;program instructions for defining one or more layout features to electrically connect the gate electrode of the third transistor of the first transistor type to the gate electrode of the fourth transistor of the second transistor type;program instructions for defining one or more layout features to electrically connect the gate electrode of the third transistor of the second transistor type to the gate electrode of the fourth transistor of the first transistor type;program instructions for defining a layout feature of a first interconnect conductive structure located within a first interconnect chip level of the semiconductor chip, the first interconnect chip level formed above a level of the semiconductor chip that includes the first, second, third, fourth, and fifth linear-shaped conductive structures;program instructions for defining a layout feature of a second interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the second interconnect conductive structure defined to be physically separate from the first interconnect conductive structure;program instructions for defining a layout feature of a third interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the third interconnect conductive structure defined to be physically separate from the first and second interconnect conductive structures;program instructions for defining a layout feature of a fourth interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the fourth interconnect conductive structure defined to be physically separate from the first, second, and third interconnect conductive structures;program instructions for defining a layout feature of a first gate contact to contact the first linear-shaped conductive structure, the first gate contact defined to extend in a vertical direction substantially perpendicular to a substrate of the semiconductor chip from the first linear-shaped conductive structure through a dielectric material to contact the second interconnect conductive structure;program instructions for defining a layout feature of a second gate contact to contact the second linear-shaped conductive structure, the second gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the second linear-shaped conductive structure through the dielectric material to contact the first interconnect conductive structure;program instructions for defining a layout feature of a third gate contact to contact the third linear-shaped conductive structure, the third gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the third linear-shaped conductive structure through the dielectric material to contact the first interconnect conductive structure;program instructions for defining a layout feature of a fourth gate contact to contact the fourth linear-shaped conductive structure, the fourth gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the fourth linear-shaped conductive structure through the dielectric material to contact the third interconnect conductive structure;program instructions for defining a layout feature of a fifth gate contact to contact the fifth linear-shaped conductive structure, the fifth gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the fifth linear-shaped conductive structure through the dielectric material to contact the fourth interconnect conductive structure,wherein the first interconnect conductive structure is defined to be physically separate from the first, fourth, and fifth gate contacts, andwherein the second interconnect conductive structure is defined to be physically separate from the second, third, fourth, and fifth gate contacts, andwherein the third interconnect conductive structure is defined to be physically separate from the first, second, third, and fifth gate contacts, andwherein the fourth interconnect conductive structure is defined to be physically separate from the first, second, third, and fourth gate contacts,the integrated circuit being part of a digital logic circuit. 29. An integrated circuit within a semiconductor chip, comprising: a first transistor of a first transistor type having a gate electrode, a first diffusion terminal of a first diffusion type, and a second diffusion terminal of the first diffusion type;a second transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;a third transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;a fourth transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type;a first transistor of a second transistor type having a gate electrode, a first diffusion terminal of a second diffusion type, and a second diffusion terminal of the second diffusion type;a second transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type;a third transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type;a fourth transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type,both the gate electrode of the first transistor of the first transistor type and the gate electrode of the first transistor of the second transistor type formed by a first linear-shaped conductive structure, the gate electrode of the first transistor of the first transistor type electrically connected to the gate electrode of the first transistor of the second transistor type through the first linear-shaped conductive structure,the gate electrode of the second transistor of the first transistor type formed by a second linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the second linear-shaped conductive structure is of the first transistor type,the gate electrode of the second transistor of the second transistor type formed by a third linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the third linear-shaped conductive structure is of the second transistor type,the gate electrode of the third transistor of the first transistor type formed as part of a fourth linear-shaped conductive structure, and the gate electrode of the fourth transistor of the second transistor type also formed as part of the fourth linear-shaped conductive structure,the gate electrode of the fourth transistor of the first transistor type formed as part of a fifth linear-shaped conductive structure, and the gate electrode of the third transistor of the second transistor type also formed as part of the fifth linear-shaped conductive structure,the first, second, third, fourth, and fifth linear-shaped conductive structures oriented to extend lengthwise in a first direction,the first linear-shaped conductive structure positioned between the second and third linear-shaped conductive structures in a second direction perpendicular to the first direction,the gate electrode of the first transistor of the first transistor type having a lengthwise centerline oriented in the first direction that is separated by a first pitch from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type, the first pitch being a distance measured in the second direction perpendicular to the first direction,the lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the first transistor type being separated from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the first transistor type by the first pitch,the gate electrode of the first transistor of the second transistor type having a lengthwise centerline oriented in the first direction that is separated by the first pitch from a lengthwise centerline oriented in the first direction of the gate electrode of the second transistor of the second transistor type,the gate electrode of the second transistor of the second transistor type having a lengthwise centerline oriented in the first direction that is separated by the first pitch from a lengthwise centerline oriented in the first direction of the gate electrode of the fourth transistor of the second transistor type,the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the first transistor type being separated by a second pitch from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the first transistor type, the second pitch being a distance measured in the second direction perpendicular to the first direction, the second pitch substantially equal to two times the first pitch,the lengthwise centerline oriented in the first direction of the gate electrode of the first transistor of the second transistor type being separated by the second pitch from a lengthwise centerline oriented in the first direction of the gate electrode of the third transistor of the second transistor type, andthe first, second, third, and fourth transistors of the first transistor type forming a first collection of transistors,the first, second, third, and fourth transistors of the second transistor type forming a second collection of transistors,the first collection of transistors separated from the second collection of transistors by an inner region that does not include a source or a drain of any transistor,the first and second transistors of the first transistor type positioned adjacent to each other, the first diffusion terminal of the first transistor of the first transistor type electrically and physically connected to the first diffusion terminal of the second transistor of the first transistor type, the first diffusion terminal of the first transistor of the first transistor type also electrically connected to a common node, the first diffusion terminal of the second transistor of the first transistor type also electrically connected to the common node,the first and second transistors of the second transistor type positioned adjacent to each other, the first diffusion terminal of the first transistor of the second transistor type electrically and physically connected to the first diffusion terminal of the second transistor of the second transistor type, the first diffusion terminal of the first transistor of the second transistor type also electrically connected to the common node, the first diffusion terminal of the second transistor of the second transistor type also electrically connected to the common node,the first diffusion terminal of the third transistor of the first transistor type electrically connected to the second diffusion terminal of the first transistor of the first transistor type,the first diffusion terminal of the fourth transistor of the first transistor type physically and electrically connected to the second diffusion terminal of the second transistor of the first transistor type,the first diffusion terminal of the third transistor of the second transistor type electrically connected to the second diffusion terminal of the first transistor of the second transistor type,the first diffusion terminal of the fourth transistor of the second transistor type physically and electrically connected to the second diffusion terminal of the second transistor of the second transistor type,the gate electrode of the third transistor of the first transistor type electrically connected to the gate electrode of the fourth transistor of the second transistor type,the gate electrode of the third transistor of the second transistor type electrically connected to the gate electrode of the fourth transistor of the first transistor type,the first linear-shaped conductive structure having a size as measured in the second direction perpendicular to the first direction that is less than 193 nanometers,the second linear-shaped conductive structure having a size as measured in the second direction perpendicular to the first direction that is less than 193 nanometers,the third linear-shaped conductive structure having a size as measured in the second direction perpendicular to the first direction that is less than 193 nanometers,the fourth linear-shaped conductive structure having a size as measured in the second direction perpendicular to the first direction that is less than 193 nanometers,the fifth linear-shaped conductive structure having a size as measured in the second direction perpendicular to the first direction that is less than 193 nanometers;a first interconnect conductive structure located within a first interconnect chip level of the semiconductor chip, the first interconnect chip level formed above a level of the semiconductor chip that includes the first, second, third, fourth, and fifth linear-shaped conductive structures;a second interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the second interconnect conductive structure physically separate from the first interconnect conductive structure;a third interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the third interconnect conductive structure physically separate from the first and second interconnect conductive structures;a fourth interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the fourth interconnect conductive structure physically separate from the first, second, and third interconnect conductive structures;a first gate contact in contact with the first linear-shaped conductive structure, the first gate contact defined to extend in a vertical direction substantially perpendicular to a substrate of the semiconductor chip from the first linear-shaped conductive structure through a dielectric material to contact the second interconnect conductive structure;a second gate contact in contact with the second linear-shaped conductive structure, the second gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the second linear-shaped conductive structure through the dielectric material to contact the first interconnect conductive structure;a third gate contact in contact with the third linear-shaped conductive structure, the third gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the third linear-shaped conductive structure through the dielectric material to contact the first interconnect conductive structure;a fourth gate contact in contact with the fourth linear-shaped conductive structure, the fourth gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the fourth linear-shaped conductive structure through the dielectric material to contact the third interconnect conductive structure;a fifth gate contact in contact with the fifth linear-shaped conductive structure, the fifth gate contact defined to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the fifth linear-shaped conductive structure through the dielectric material to contact the fourth interconnect conductive structure,wherein the first interconnect conductive structure is defined to be physically separate from the first, fourth, and fifth gate contacts, andwherein the second interconnect conductive structure is defined to be physically separate from the second, third, fourth, and fifth gate contacts, andwherein the third interconnect conductive structure is defined to be physically separate from the first, second, third, and fifth gate contacts, andwherein the fourth interconnect conductive structure is defined to be physically separate from the first, second, third, and fourth gate contacts; anda sixth linear-shaped conductive structure that does not form a gate electrode of any transistor, the sixth linear-shaped conductive structure located in the level of the semiconductor chip that includes the first, second, third, fourth, and fifth linear-shaped conductive structures,the sixth linear-shaped conductive structure positioned in a side-by-side manner with multiple adjacently positioned linear-shaped conductive structures that collectively form gate electrodes of two adjacently positioned transistors of the first transistor type and gate electrodes of two adjacently positioned transistors of the second transistor type,at least one of the multiple adjacently positioned linear-shaped conductive structures being a multiple gate electrode forming linear-shaped conductive structure that forms both a gate electrode of one of the two adjacently positioned transistors of the first transistor type and a gate electrode of one of the two adjacently positioned transistors of the second transistor type,the sixth linear-shaped conductive structure and each of the multiple adjacently positioned linear-shaped conductive structures having a corresponding lengthwise centerline oriented in the first direction,the sixth linear-shaped conductive structure having a total length as measured in the first direction at least equal to a total length of the multiple gate electrode forming linear-shaped conductive structure as measured in the first direction,the lengthwise centerline of the sixth linear-shaped conductive structure separated from each lengthwise centerline of each of the multiple adjacently positioned linear-shaped conductive structures by a distance as measured in the second direction substantially equal to the first pitch,the sixth linear-shaped conductive structure defined to extend lengthwise from a first end to a second end,the first end of the sixth linear-shaped conductive structure substantially aligned with an end of at least one of the multiple adjacently positioned linear-shaped conductive structures that forms the gate electrode of one of the two adjacently positioned transistors of the first transistor type,the second end of the sixth linear-shaped conductive structure substantially aligned with an end of at least one of the multiple adjacently positioned linear-shaped conductive structures that forms the gate electrode of one of the two adjacently positioned transistors of the second transistor type,the integrated circuit being part of a digital logic circuit, andthe integrated circuit included within a single layout cell. 30. The integrated circuit within the semiconductor chip as recited in claim 29, wherein the first linear-shaped conductive structure has a size as measured in the second direction perpendicular to the first direction that is less than 34 nanometers, wherein the second linear-shaped conductive structure has a size as measured in the second direction perpendicular to the first direction that is less than 34 nanometers,wherein the third linear-shaped conductive structure has a size as measured in the second direction perpendicular to the first direction that is less than 34 nanometers,wherein the fourth linear-shaped conductive structure has a size as measured in the second direction perpendicular to the first direction that is less than 34 nanometers,wherein the fifth linear-shaped conductive structure has a size as measured in the second direction perpendicular to the first direction that is less than 34 nanometers,wherein the sixth linear-shaped conductive structure has a size as measured in the second direction perpendicular to the first direction that is less than 34 nanometers.
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