Apparatus and method for encoding data for storage in multi-level nonvolatile memory
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G11C-029/00
G06F-011/10
G06F-011/16
출원번호
US-0217675
(2014-03-18)
등록번호
US-8856622
(2014-10-07)
발명자
/ 주소
Ramamoorthy, Aditya
Wu, Zining
Sutardja, Pantas
출원인 / 주소
Marvell World Trade Ltd.
인용정보
피인용 횟수 :
17인용 특허 :
32
초록▼
A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels. The encoder generates first data for storage in first memory cells. For first and second subsets of cells of the first memory cells, the first da
A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels. The encoder generates first data for storage in first memory cells. For first and second subsets of cells of the first memory cells, the first data is stored at first and second levels, respectively. Measurable values of the first subset of cells are characterized by a first probability density function having a first width. Measurable values of the second subset of cells are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first data such that a size of the first subset of cells is less than a size of the second subset of cells. The decoder decodes encoded data from the memory.
대표청구항▼
1. A controller for a nonvolatile memory having memory cells that are each configured to store data using more than two levels, the controller comprising: an encoder configured to generate first data for storage in first memory cells of the memory cells, wherein for a first subset of cells of the fi
1. A controller for a nonvolatile memory having memory cells that are each configured to store data using more than two levels, the controller comprising: an encoder configured to generate first data for storage in first memory cells of the memory cells, wherein for a first subset of cells of the first memory cells, the first data is stored at a first level of the more than two levels,measurable values of the first subset of cells are characterized by a first probability density function having a first width,for a second subset of cells of the first memory cells, the first data is stored at a second level of the more than two levels,measurable values of the second subset of cells are characterized by a second probability density function having a second width,the first width of the first probability density function is greater than the second width of the second probability density function, andthe encoder is configured to generate the first data such that a size of the first subset of cells is less than a size of the second subset of cells; anda decoder configured to (i) receive, from the nonvolatile memory, encoded data, and (ii) decode the encoded data to produce decoded data. 2. The controller of claim 1, wherein the measurable values are threshold voltages. 3. The controller of claim 1, further comprising a modulator configured to modulate the first data from the encoder to determine levels at which to program the first memory cells. 4. The controller of claim 3, further comprising a demodulator configured to generate the encoded data by demodulating modulated data stored in the nonvolatile memory. 5. The controller of claim 4, wherein the demodulator includes an analog-to-digital converter. 6. The controller of claim 5, wherein the memory cells are each configured to store data using a first number of levels, wherein the analog-to-digital converter is configured to generate one of a second number of digital values in response to each of the memory cells, and wherein the second number is greater than the first number. 7. The controller of claim 1, further comprising a second encoder configured to encode user data to create second data, wherein the encoder generates the first data based on the second data. 8. The controller of claim 7, wherein the encoder includes a low-density parity-check encoder and wherein the second encoder includes a Reed-Solomon encoder. 9. The controller of claim 7, further comprising a second decoder configured to recover the user data based on the decoded data. 10. The controller of claim 9, wherein the decoder includes a trellis coded modulation decoder and wherein the second decoder includes a Reed-Solomon decoder. 11. The controller of claim 10, wherein the decoder is configured to operate on rows of a block of data from the nonvolatile memory, and wherein the second decoder is configured to operate on columns of the block of data. 12. The controller of claim 1, wherein the nonvolatile memory is flash memory. 13. An integrated circuit comprising the controller of claim 1. 14. A memory system comprising the integrated circuit of claim 13 and further comprising the nonvolatile memory. 15. A method of operating a controller for a nonvolatile memory having memory cells that are each configured to store data using more than two levels, the method comprising: generating first data for storage in first memory cells of the memory cells, wherein for a first subset of cells of the first memory cells, the first data is stored at a first level of the more than two levels,measurable values of the first subset of cells are characterized by a first probability density function having a first width,for a second subset of cells of the first memory cells, the first data is stored at a second level of the more than two levels,measurable values of the second subset of cells are characterized by a second probability density function having a second width,the first width of the first probability density function is greater than the second width of the second probability density function, andthe first data is generated such that a size of the first subset of cells is less than a size of the second subset of cells;receiving, from the nonvolatile memory, encoded data; anddecoding the encoded data to produce decoded data. 16. The method of claim 15, wherein the measurable values are threshold voltages. 17. The method of claim 15, further comprising modulating the first data to determine levels at which to program the first memory cells. 18. The method of claim 17, further comprising generating the encoded data by demodulating modulated data stored in the nonvolatile memory. 19. The method of claim 18, wherein the memory cells are each configured to store data using a first number of levels, wherein the method comprises generating one of a second number of digital values in response to each of the memory cells, and wherein the second number is greater than the first number. 20. The method of claim 15, further comprising encoding user data to create second data, wherein the first data is generated based on the second data. 21. The method of claim 20, wherein the first data is generated using a low-density parity-check encoding and wherein the second data is generated using Reed-Solomon encoding. 22. The method of claim 20, further comprising recovering the user data based on the decoded data. 23. The method of claim 22, wherein the decoded data is produced using trellis coded modulation decoding and wherein the user data is recovered using Reed-Solomon decoding. 24. The method of claim 23, further comprising: operating the trellis coded modulation decoding on rows of a block of data from the nonvolatile memory; andoperating the Reed-Solomon decoding on columns of the block of data.
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