$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Apparatus and method for encoding data for storage in multi-level nonvolatile memory 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-029/00
  • G06F-011/10
  • G06F-011/16
출원번호 US-0217675 (2014-03-18)
등록번호 US-8856622 (2014-10-07)
발명자 / 주소
  • Ramamoorthy, Aditya
  • Wu, Zining
  • Sutardja, Pantas
출원인 / 주소
  • Marvell World Trade Ltd.
인용정보 피인용 횟수 : 17  인용 특허 : 32

초록

A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels. The encoder generates first data for storage in first memory cells. For first and second subsets of cells of the first memory cells, the first da

대표청구항

1. A controller for a nonvolatile memory having memory cells that are each configured to store data using more than two levels, the controller comprising: an encoder configured to generate first data for storage in first memory cells of the memory cells, wherein for a first subset of cells of the fi

이 특허에 인용된 특허 (32)

  1. Li,Yan; Pham,Long, Apparatus for programming of multi-state non-volatile memory using smart verify.
  2. Perego,Richard; Ware,Fred; Tsern,Ely, Configurable width buffered module.
  3. Perego,Richard; Ware,Fred; Tsern,Ely; Hampel,Craig, Configurable width buffered module having a bypass circuit.
  4. Ware,Fred; Perego,Richard; Tsern,Ely, Configurable width buffered module having switch elements.
  5. Masumoto, Masayuki; Kurata, Kazushi; Tsuruta, Hideyo, Decoding apparatus and encoding apparatus with specific bit sequence deletion and insertion.
  6. Hans-Werner Knefel DE, Error recognition in a storage system.
  7. Yoshida Hideo (Kanagawa JPX), Error-correction encoding and decoding system.
  8. You,Byoung Sung, Flash memory device with reduced access time.
  9. Eidson,Donald Brian; Krieger,Abraham; Murali,Ramaswamy, Iterative decoder employing multiple external code error checks to lower the error floor.
  10. Shinagawa,Chiaki; Kanamori,Motoki; Shiraishi,Atsushi, Memory card.
  11. Lester, Robert A.; MacLaren, John M.; Ferguson, Patrick L.; Larson, John E., Memory data verify operation.
  12. Takeuchi Ken,JPX ; Tanaka Tomoharu,JPX, Memory system.
  13. Horowitz,Mark A.; Best,Scott C.; Stonecypher,William F., Method and apparatus for multi-level signaling.
  14. Zaleski, II,Kenneth G; Hebsgaard,Anders, Method and apparatus for performing trellis coded modulation of signals for transmission on a TDMA channel of a cable network.
  15. Vafai Manouchehr ; Rostoker Michael D., Method and apparatus for significantly improving the reliability of multilevel memory architecture.
  16. Micheloni, Rino; Campardo, Giovanni, Method and circuit for generating reference voltages for reading a multilevel memory cell.
  17. Guterman Daniel C. ; Fong Yupin Kawing, Multi-state memory.
  18. Guterman,Daniel C.; Fong,Yupin Kawing, Multi-state memory.
  19. Guterman,Daniel C.; Fong,Yupin Kawing, Multi-state memory.
  20. Guterman,Daniel C.; Fong,Yupin Kawing, Multi-state memory.
  21. Li,Yan; Fong,Yupin Kawing; Miwa,Toru, Non-volatile memory and control with improved partial page program capability.
  22. Li,Yan; Fong,Yupin Kawing; Miwa,Toru, Non-volatile memory and control with improved partial page program capability.
  23. Tanzawa, Toru; Atsumi, Shigeru, Non-volatile semiconductor memory.
  24. Tanzawa, Toru; Atsumi, Shigeru, Non-volatile semiconductor memory.
  25. Mori,Toshiki, Non-volatile semiconductor memory device and method for reading the same.
  26. Kang, Hee Bok, Nonvolatile ferroelectric memory device and method for storing multiple bit using the same.
  27. Noda,Satoshi; Kozakai,Kenji; Matsushita,Toru; Jono,Yusuke, Nonvolatile memory and nonvolatile memory apparatus.
  28. Tanaka, Tomoharu; Ohuchi, Kazunori; Tanzawa, Toru; Takeuchi, Ken, Nonvolatile semiconductor memory device.
  29. Kubo,Kazuo; Yoshida,Hideo; Ichibangase,Hiroshi, Optical transmission system, fec multiplexer, fec multiplexer/separator, and error correction method.
  30. Micheloni, Rino; Losavio, Aldo, Self-repair method via ECC for nonvolatile memory devices, and relative nonvolatile memory device.
  31. Riho,Yoshiro; Ito,Yutaka, Semiconductor device and testing method for same.
  32. Kitayama Seishi (Tokyo JPX) Yato Fumihiro (Tokyo JPX) Kurematsu Akira (Tokyo JPX), Voice encoding and decoding device.

이 특허를 인용한 특허 (17)

  1. Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W.; Jaser, Ihab, Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system.
  2. Marelli, Alessia; Micheloni, Rino, Background reference positioning and local reference positioning using threshold voltage shift read.
  3. Seol, Changkyu; Kong, Junjin; Son, Hong Rak; Yoo, Younggeon, Code modulation encoder and decoder, memory controller including them, and flash memory system.
  4. Micheloni, Rino; Marelli, Alessia; Norrie, Christopher I. W., High quality log likelihood ratios determined using two-index look-up table.
  5. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W., Layer specific LDPC decoder.
  6. Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W., Layer specific attenuation factor LDPC decoder.
  7. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W.; Jaser, Ihab, Memory controller and integrated circuit device for correcting errors in data read from memory cells.
  8. Sugiyama, Mitsuhiko; Ueki, Katsuhiko, Memory system.
  9. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W., Method and apparatus for layer-specific LDPC decoding.
  10. Brown, David Alan; Onufryk, Peter Z.; Talledo, Cesar, Method and apparatus for translated routing in an interconnect switch.
  11. Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Method and apparatus with program suspend using test mode.
  12. Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Nonvolatile memory controller and method for erase suspend management that increments the number of program and erase cycles after erase suspend.
  13. Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Nonvolatile memory system with erase suspend circuit and method for erase suspend management.
  14. Micheloni, Rino, Nonvolatile memory system with program step manager and method for program step management.
  15. Micheloni, Rino; Marelli, Alessia; Bates, Stephen, Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction.
  16. Micheloni, Rino; Marelli, Alessia; Crippa, Luca, System and method for memory block pool wear leveling.
  17. Graumann, Peter John Waldemar; Fard, Saeed Fouladi, Variable T BCH encoding.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로