최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0909150 (2010-10-21) |
등록번호 | US-RE45223 (2014-10-28) |
우선권정보 | DE-197 04 728 (1997-02-08) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 0 인용 특허 : 571 |
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.
1. A method for controlling data processing by an integrated circuit that includes a plurality of data processing elements that are arranged for at least one of arithmetically and logically processing data using a sequence of commands, the sequence including jumps, the method comprising: for each of
1. A method for controlling data processing by an integrated circuit that includes a plurality of data processing elements that are arranged for at least one of arithmetically and logically processing data using a sequence of commands, the sequence including jumps, the method comprising: for each of a plurality of the processing elements that each include at least one corresponding register: predefining at least one corresponding configuration command; andstoring each of the at least one corresponding configuration command in one of the at least one register corresponding to the processing element;processing data in at least one first processing element;obtaining at least one of a comparison, a sign, a carryover, and an error state during the processing of the data in the at least one first processing element;in response to the at least one of the comparison, the sign, the carry-over, and the error state, generating for the at least one second processing element at least one first synchronization signal within a data stream during runtime;processing data in at least one second processing element in a stream-like manner; andin response to the at least one first synchronization signal, selecting at least one particular command from the stored configuration commands in order to control a jump in the sequence. 2. A Field Programmable Gate Array integrated circuit, comprising: a multi-dimensionally arranged configurable element structure including configurable elements; an interconnection system for interconnecting the configurable elements; andat least one of a unit and an interface for configuring the configurable elements;wherein:each of at least one of the configurable elements:is adapted for data processing;includes:at least one configuration register adapted for receiving and storing therein during runtime at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection;at least two data inputs and at least one data output connected to the interconnection system;at least one arithmetic-logic-unit; and at least one status information input from the interconnection system; and is adapted for being configured by the at least one of the unit and the interfacewith at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code. 3. The Field Programmable Gate Array integrated circuit according to claim 2, wherein configuration registers of different configurable elements are adapted for receiving therein different configuration codes, for the different configurable elements to be accordingly simultaneously configured with different at least one of functions and interconnections. 4. The Field Programmable Gate Array integrated circuit according to claim 2, wherein the at least one of the configurable elements comprises a configuration interface input for receiving from at least one other of the configurable element the at least one configuration code via the interconnection system. 5. The Field Programmable Gate Array integrated circuit according to claim 4, wherein the Field Programmable Gate Array is adapted for the at least one configuration code to be generated at runtime. 6. The Field Programmable Gate Array integrated circuit according to claim 4, wherein the Field Programmable Gate Array is adapted for the at least one configuration code to be the processing result of the at least one other of the configurable elements. 7. The Field Programmable Gate Array integrated circuit according to claim 4, wherein the at least one of the configurable elements comprises at least one status information output to the interconnection system. 8. The Field Programmable Gate Array integrated circuit according to either of claims 4 and 7, wherein the at least one of the configurable elements comprises at least one adder. 9. The Field Programmable Gate Array integrated circuit according to claim 8, further comprising a feed back channel for feeding back a result of the at least one adder to an operand input of the at least one adder via a multiplexer. 10. The Field Programmable Gate Array integrated circuit according to claim 8, wherein the at least one of the configurable elements comprises at least one comparator. 11. The Field Programmable Gate Array integrated circuit according to claim 4, wherein the at least one of the configurable elements comprises: at least one adder; at least one comparator adapted for generating the status information; and at least one output for providing the status information to the interconnection system. 12. The Field Programmable Gate Array integrated circuit according to claim 4, wherein the status information is the equal status. 13. The Field Programmable Gate Array integrated circuit according to claim 8, wherein the at least one of the configurable elements comprises at least one state-machine. 14. The Field Programmable Gate Array integrated circuit according to claim 8, wherein the at least one of the configurable elements is adapted for inclusion therein of the status information generated by the at least one adder. 15. The Field Programmable Gate Array integrated circuit according to claim 14, wherein the status information is the equal status. 16. A Field Programmable Gate Array integrated circuit comprising: a multi-dimensionally arranged configurable element structure including a plurality of configurable elements; an interconnection system for interconnecting the configurable elements; and at least one of a unit and an interface for configuring and reconfiguring the configurable elements;wherein each of at least one of the configurable elements: is adapted for data processing; includes: at least two data inputs and at least one data output connected to the interconnection system;at least one arithmetic-logic-unit; a configuration interface input; and at least one configuration register adapted for receiving, during runtime, from at least one other of the configurable elements, and via the configuration interface input and the interconnection system, and storing during runtime, at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection; andis adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code. 17. The Field Programmable Gate Array integrated circuit according to claim 16, wherein the Field Programmable Gate Array is adapted for the at least one configuration code to be generated by the at least one other of the configurable elements at runtime. 18. The Field Programmable Gate Array integrated circuit according to claim 17, wherein the Field Programmable Gate Array is adapted for the at least one configuration code to be transmitted at runtime. 19. The Field Programmable Gate Array integrated circuit according to claim 18, wherein the Field Programmable Gate Array is adapted for the at least one configuration code to be the processing result of the at least one other of the configurable elements. 20. The Field Programmable Gate Array integrated circuit according to claim 17, wherein the at least one of the configurable elements comprises at least one status information output to the interconnection system. 21. The Field Programmable Gate Array integrated circuit according to any one of claims 17 and 20, wherein the at least one of the configurable elements comprises at least one adder. 22. The Field Programmable Gate Array integrated circuit according to claim 21, further comprising a feed back channel for feeding back a result of the a least one adder to an operand input of the at least one adder via a multiplexer. 23. The Field Programmable Gate Array integrated circuit according to claim 21, wherein the at least one of the configurable elements comprises at least one comparator. 24. The Field Programmable Gate Array integrated circuit according to claim 17, wherein the at least one of the configurable elements comprises: at least one adder; at least one comparator adapted for generating the status information; and at least one output for providing the status information to the interconnection system. 25. The Field Programmable Gate Array integrated circuit according to claim 24, wherein the status information is an equal status. 26. The Field Programmable Gate Array integrated circuit according to claim 21, wherein the at least one of the configurable elements comprises at least one state-machine. 27. The Field Programmable Gate Array integrated circuit according to claim 21, wherein the at least one adder is adapted for generating status information. 28. The Field Programmable Gate Array integrated circuit according to claim 27, wherein the status information is an equal status. 29. A configurable element arrangement adapted for implementation in an integrated circuit, the integrated circuit comprising: a multi-dimensionally arranged configurable element structure including a plurality of configurable elements;an interconnection system for interconnecting the configurable elements; and at least one of a unit and an interface for configuring the configurable elements; wherein each of at least one of the configurable elements:comprises: at least two data inputs and at least one data output connected to the interconnection system;at least one arithmetic-logic-unit; a configuration interface input; and at least one configuration register adapted for receiving, during runtime, via the configuration interface input and the interconnection system, and from a unit other than the at least one of the unit and the interface, and storing during runtime, at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection;is adapted for being configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; andis adapted for data processing. 30. The configurable element arrangement according to claim 29, wherein the configurable element is adapted for receiving at runtime the at least one configuration code from at least one other configurable element. 31. The configurable element arrangement according to claim 30, wherein the configurable element arrangement is adapted for the at least one configuration code from the at least one other configurable element to be generated at runtime. 32. The configurable element arrangement according to claim 30, wherein the configurable element arrangement is adapted for the at least one configuration code from the at least one other configurable element to be a processing result of the at least one other configurable element. 33. The configurable element arrangement according to claim 29, further comprising at least one status information input from the interconnection system. 34. The configurable element arrangement according to claim 29, further comprising at least one status information output to the interconnection system. 35. The configurable element arrangement according to any one of claims 29 and 34, further comprising at least one adder. 36. The configurable element arrangement according to claim 35, further comprising a feed back channel for feeding back, via a multiplexer, a result of the at least one adder to an operand input of the at least one adder. 37. The configurable element arrangement according to claim 35, further comprising at least one comparator. 38. The configurable element arrangement according to claim 35, further comprising at least one state-machine. 39. The configurable element arrangement according to claim 29, further comprising: at least one adder adapted for generating status information; and at least one status information output for outputting the status information to the interconnection system. 40. The configurable element arrangement according to claim 29, wherein the status information is an equal status. 41. The configurable element arrangement according to claim 39, wherein the configurable elements are implemented in a Field Programmable Gate Array integrated circuit. 42. The configurable element arrangement according to claim 39, wherein the configurable elements are implemented in a runtime configurable Field Programmable Gate Array. 43. The configurable element arrangement according to claim 39, wherein the configurable elements are implemented in a configurable processor integrated circuit. 44. The configurable element arrangement according to claim 39, wherein the configurable elements are implemented in a runtime configurable processor integrated circuit. 45. The configurable element arrangement according to claim 39, wherein the configurable elements are implemented in one of a configurable arithmetic processor integrated circuit and a configurable arithmetic coprocessor integrated circuit. 46. The configurable element arrangement according to claim 29, further comprising: at least one adder adapted for generating status information; at least one comparator; andat least one status information output for outputting the status information to the interconnection system. 47. The configurable element arrangement according to claim 46, wherein the status information is an equal status. 48. The configurable element arrangement according to claim 46, wherein the configurable elements are implemented in a Field Programmable Gate Array integrated circuit. 49. The configurable element arrangement according to claim 46, wherein the configurable elements are implemented in a runtime configurable Field Programmable Gate Array integrated circuit. 50. The configurable element arrangement according to claim 46, wherein the configurable elements are implemented in a configurable processor integrated circuit. 51. The configurable element arrangement according to claim 46, wherein the configurable elements are implemented in a runtime configurable processor integrated circuit. 52. The configurable element arrangement according to claim 46, wherein the configurable elements are implemented in one of a configurable arithmetic processor integrated circuit and a configurable arithmetic coprocessor integrated circuit. 53. A data processing integrated circuit, comprising: a multi-dimensionally arranged configurable element structure including a plurality of configurable elements; at least one of the configurable elements: comprises: at least two data inputs and at least one data output connected to the interconnection system;at least one arithmetic-logic-unit; a configuration interface input; and at least one configuration register adapted for receiving, during runtime and via the configuration interface input and the interconnection system, and storing during runtime, at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection;is adapted for being configured, by (a) the at least one of the unit and the interface and (b) at least one other of the configurable elements, and with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; andadapted for data processing. 54. The data processing integrated circuit according to claim 53, wherein the data processing integrated circuit is adapted for the at least one configuration code to be a processing result of the at least one other of the configurable elements. 55. The data processing integrated circuit according claim 53, wherein the each of the at least one of the configurable elements comprises at least one status information output to the interconnection system. 56. The data processing integrated circuit according to any one of claims 53 and 55, wherein the each of the at least one of the configurable elements comprises at least one adder. 57. The data processing integrated circuit according to claim 56, comprising a feed back channel for feeding back a result of the at least one adder to an operand input of the at least one adder via a multiplexer. 58. The data processing integrated circuit according claim 56, wherein the each of the at least one of the configurable elements comprises at least one comparator. 59. The data processing integrated circuit according to claim 56, wherein the each of the at least one of the configurable elements comprises at least one state-machine. 60. The data processing integrated circuit according to claim 53, wherein the each of the at least one of the configurable elements comprises: at least one adder adapted for generating status information; and at least one status information output adapted for providing the status information to the interconnection system. 61. The data processing integrated circuit according to claim 60, wherein the status information is an equal status. 62. The data processing integrated circuit according to claim 53, wherein the each of the at least one of the configurable elements comprises: at least one adder; at least one comparator adapted for generating status information; and at least one status information output adapted for providing the status information to the interconnection system. 63. The data processing integrated circuit according to claim 62, wherein the status information is an equal status. 64. A data processing integrated circuit comprising: configurable elements arranged in a multi-dimensional pattern;an interconnection system for interconnecting the configurable elements; andat least one of a unit and an interface for configuring the configurable elements; wherein each of at least some of the configurable elements: comprises: at least one arithmetic unit; at least two operand registers; at least one result register; at least one input interface to the interconnection system for receiving status information generated by another of the configurable elements from the interconnection system;at least one configuration data input; and at least one configuration register adapted for receiving, at runtime and via the at least one configuration data input, and storing during runtime, at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection;is adapted for being configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; andis adapted to process the at least two operands arithmetically according to the at least one configuration code and received status information. 65. The data processing integrated circuit according to claim 64, wherein the each of the at least some of the configurable elements is adapted for the receipt of the at least one configuration code to be from at least one other of the configurable elements at runtime. 66. The data processing integrated circuit according to claim 64, wherein the each of the at least some of the configurable elements is adapted for the receipt of the at least one configuration code to be from at least one other of the configurable elements via the interconnection system. 67. The data processing integrated circuit according to claim 64, wherein the at least one configuration data input is adapted for obtaining the at least one configuration code from at least one other of the configurable elements at runtime. 68. The data processing integrated circuit according to claim 67, wherein the at least one configuration data input is connected to the at least one other of the configurable elements via the interconnection system. 69. The data processing integrated circuit according to any of claims 67 and 68, wherein the data processing integrated circuit is adapted for the at least one configuration code received by the each of the at least one of the configurable elements to be generated by at least one other of the configurable elements at runtime. 70. The data processing integrated circuit according to claim 64, wherein the at least one configuration data input is adapted to be connected to at least one other of the configurable elements at runtime via the interconnection system. 71. The data processing integrated circuit according to claim 64, wherein the at least one configuration data input is interconnected to a plurality of configurable elements via the interconnection system. 72. The data processing integrated circuit according to claim 64, wherein the each of the at least some of the configurable elements is adapted to be configured by the at least one of the unit and the interface, and is adapted for the at least one configuration code to be received at the input interface at runtime via the interconnection system from at least one other of the configurable elements. 73. The data processing integrated circuit according to any one of claims 65, 67, and 72, wherein the each of the at least some of the configurable elements comprises at least one output interface to the interconnection system for sending status information generated by the at least one other of the configurable elements via the interconnection system to another of the configurable elements. 74. The data processing integrated circuit according to claim 73, wherein the data processing integrated circuit is adapted for the status information to be generated by an adder within at least one arithmetic unit. 75. The data processing integrated circuit according to claim 74, wherein said adder has a feed back channel for feeding back the result of said adder to an operand input of said adder via a multiplexer. 76. The data processing integrated circuit according to claim 64, wherein the status information is an equal status of a comparator located inside the at least some of the configurable elements. 77. The data processing integrated circuit according to claim 64, wherein the data processing integrated circuit is one of a configurable arithmetic processor and a configurable arithmetic coprocessor. 78. The data processing integrated circuit according to claim 64, wherein the data processing integrated circuit is configurable at runtime. 79. The data processing integrated circuit according to claim 74, wherein the data processing integrated circuit is one of a configurable arithmetic processor and a configurable arithmetic coprocessor. 80. The data processing integrated circuit according to claim 74, wherein the data processing integrated circuit is configurable at runtime. 81. A Field Programmable Gate Array integrated circuit comprising: configurable elements arranged in a multi-dimensional pattern; an interconnection system for interconnecting the configurable elements; and at least one of a unit and an interface for configuring the configurable elements; wherein each of at least some of the configurable elements: comprises: at least one arithmetic unit; at least two operand registers; at least one result register; at least one input interface to the interconnection system for receiving status information generated by another of the configurable elements from the interconnection system;at least one configuration data input; and at least one configuration register adapted for receiving, during runtime and via the at least one configuration data input, and storing during runtime at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection;is adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; andis adapted to process the at least two operands arithmetically according to the configuration data and received status information. 82. The data processing integrated circuit according to claim 81, wherein the each of the at least some of the configurable elements is adapted for the runtime receipt of the at least one configuration code to be from at least one other of the configurable elements. 83. The data processing integrated circuit according to claim 81, wherein the each of the at least some of the configurable elements is adapted for the runtime receipt of the at least one configuration code to be from at least one other of the configurable elements via the interconnection system. 84. The data processing integrated circuit according to claim 81, wherein the at least one configuration data input is adapted for obtaining the at least one configuration code from at least one other of the configurable elements at runtime. 85. The Data Processing Integrated Circuit according to claim 84, wherein the at least one configuration data input is connected to the at least one other of the configurable elements via the interconnection system. 86. The data processing integrated circuit according to any of claims 84 and 85, wherein the data processing integrated circuit is adapted for the at least one configuration code to be generated by at least one other of the configurable elements at runtime. 87. The data processing integrated circuit according to claim 81, wherein the at least one configuration data input is adapted for connection to at least one other of the configurable elements at runtime via the interconnection system. 88. The data processing integrated circuit according to claim 81, wherein the at least one configuration data input is interconnected to a plurality of configurable elements via the interconnection system. 89. The data processing integrated circuit according to claim 81, wherein the each of the at least some of the configurable elements is adapted to be configured by the at least one of the unit and the interface and is adapted for the runtime receipt of the at least one configuration code to be from at least one other of the configurable elements. 90. The data processing integrated circuit according to any one of claims 82, 84, and 89, wherein the each of the at least some of the configurable elements comprises at least one output interface to the interconnection system for sending status information generated by the at least one other of the configurable elements via the interconnection system to another of the configurable elements. 91. The data processing integrated circuit according to claim 90, wherein the data processing integrated circuit is adapted for the status information to be generated by an adder within at least one arithmetic unit. 92. The data processing integrated circuit according to claim 91, wherein said adder has a feed back channel for feeding back the result of said adder to an operand input of said adder via a multiplexer. 93. The data processing integrated circuit according to claim 91, wherein the status information is generated by a comparator. 94. The data processing integrated circuit according to claim 93, wherein the status information is an equal status of a comparator located inside the at least some of the configurable elements. 95. A Field Programmable Gate Array integrated circuit comprising: configurable elements arranged in a multi-dimensional pattern; an interconnection system for interconnecting the configurable elements; and at least one of a unit and an interface for configuring the configurable elements; wherein each of at least some of the configurable elements:is adapted to receive at least one configuration code from said at least one of the unit and the interface;comprises: at least one arithmetic unit; at least two operand registers; at least one result register; at least one configuration data input for receiving at runtime, from at least one other of the configurable elements and via the interconnection system, at least one additional configuration code, each of the at least one additional configuration code representing only one of a single respective function and a single respective interconnection of the configurable element; andat least one configuration register adapted for storing therein at runtime the at least one additional configuration code;is adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one additional configuration code; andis adapted to process at least two operands of the at least two operand registers arithmetic-logically according to the at least one additional configuration code received from the configuration data input and the at least one configuration code provided by said at least one of the unit and the interface. 96. The Field Programmable Gate Array integrated circuit according to claim 95, wherein the each of at least some of the configurable elements comprises at least one input interface to the interconnection system for receiving status information generated by another of the configurable elements from the interconnection system. 97. The Field Programmable Gate Array integrated circuit according to anyone of claims 95 and 96 wherein, the each of at least some of the configurable elements comprises at least one output interface to the interconnection system for sending status information generated by the configurable element via the interconnection system to at least one other of the configurable elements. 98. The Field Programmable Gate Array integrated circuit according to claim 97, wherein the at least some of the configurable elements are adapted to process the at least two operands arithmetic-logically additionally according to the statns information. 99. The Field Programmable Gate Array integrated circuit according to claim 98, wherein the status information is generated by an adder inside the at least one arithmetic unit. 100. The Field Programmable Gate Array integrated circuit according to claim 99, wherein said adder has a feed back channel for feeding back a result of said adder to an operand input of said adder via a multiplexer. 101. The Field Programmable Gate Array integrated circuit according to claim 99, wherein the status information is generated by a comparator inside the at least some of the configurable elements. 102. The Field Programmable Gate Array integrated circuit according to claim 101, wherein the status information is an equal status of a comparator located inside the each of the at least some of the configurable elements. 103. A data processing integrated circuit comprising: configurable elements arranged in a multi-dimensional pattern;an interconnection system for interconnecting the configurable elements; and at least one of a unit and an interface for configuring the configurable elements; wherein each of at least some of the configurable elements: is adapted to receive at least one configuration code from said at least one of the unit and the interface;comprises: at least one arithmetic unit; at least two operand registers; at least one result register; at least one configuration data input for receiving at runtime, from at least one other of the configurable elements and via the interconnection system, at least one additional configuration code, each of the at least one additional configuration code representing only one of a single respective function and a single respective interconnection of the configurable element; andat least one configuration register adapted for storing therein at runtime the at least one additional configuration code; is adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one additional configuration code; andis adapted to process at least two operands of the at least two operand registers arithmetic-logically according to the at least one additional configuration code received from the configuration data input and the at least one configuration code provided by said at least one of the unit and the interface. 104. The data processing integrated circuit according to claim 103, wherein the each of at least some of the configurable elements comprises at least one input interface to the interconnection system for receiving status information generated by another of the configurable elements from the interconnection system. 105. The data processing integrated circuit according to anyone of claims 103 and 104 wherein, the each of at least some of the configurable elements comprises at least one output interface to the interconnection system for sending status information generated by the configurable element via the interconnection system to at least one other of the configurable elements. 106. The data processing integrated circuit according to claim 105, wherein the at least some of the configurable elements are adapted to process the at least two operands arithmetic-logically additionally according to the status information. 107. The data processing integrated circuit according to claim 106, wherein the data processing integrated circuit is adapted for the status information to be generated by an adder inside the at least one arithmetic unit. 108. The data processing integrated circuit according to claim 107, wherein said adder has a feed back channel for feeding back a result of said adder to an operand input of said adder via a multiplexer. 109. The data processing integrated circuit according to claim 107, wherein the data processing integrated circuit is adapted for the status information to be generated by a comparator inside the at least some of the configurable elements. 110. The data processing integrated circuit according to claim 109, wherein the status information is an equal status of a comparator located inside the each of the at least some of the configurable elements. 111. The data processing integrated circuit according to claim 109, wherein the data processing integrated circuit is one of a configurable arithmetic processor integrated circuit and a configurable arithmetic coprocessor integrated circuit. 112. The data processing integrated circuit according to claim 109, wherein the data processing integrated circuit is configurable at runtime. 113. The data processing integrated circuit according to claim 107, wherein the data processing integrated circuit is one of a configurable arithmetic processor integrated circuit and a configurable arithmetic coprocessor integrated circuit. 114. The data processing integrated circuit according to claim 107, wherein the data processing integrated circuit is configurable at runtime. 115. A runtime configurable integrated data processing circuit, comprising: a plurality of configurable elements arranged in a multi-dimensional structure; and a configurable interconnection for connecting the plurality of configurable elements; wherein: each of at least some of the plurality of configurable elements: includes: at least two operand registers for receiving operand data from the configurable interconnection;at least one result register for transmitting result data to the configurable interconnection;at least one arithmetic unit; at least one configuration input for configuring at least an operation performed by the at least one arithmetic unit;at least one multiplexer located between at least one of the operand registers and the arithmetic unit, the at least one of the operand registers being adapted for feeding at least a first one of inputs of the multiplexer; andat least one feedback from the at least one result register to at least one input of the at least one multiplexer adapted for feeding result data back to the at least one arithmetic unit; andis adapted for transmitting at runtime its result as at least one configuration code to the configuration input of at least one other of the at least some of the plurality of configurable elements via the interconnection;each of the at least one other of the at least some of the plurality of configurable elements:includes at least one configuration register adapted for storing therein during runtime the at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection; andis adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; andat least some of the configurable elements are adapted for processing data according to their configuration. 116. The runtime configurable integrated data processing circuit according to claim 115, wherein at least some of the at least some of the plurality of configurable elements comprise at least one respective configuration input adapted for configuring an interconnection of the at least some of the at least some of the plurality of the configurable elements to at least one other of the configurable elements. 117. The runtime configurable integrated data processing circuit according to any one of claims 115 and 116, wherein the runtime configurable integrated data processing circuit is a Field Programmable Gate Array Integrated Circuit (FPGA). 118. A runtime configurable integrated data processing circuit, comprising: a plurality of configurable elements arranged in a multi-dimensional structure; and a configurable interconnection for connecting the plurality of configurable elements; wherein: each of at least some of the plurality of configurable elements: includes: at least two operand registers; at least one result register;at least one arithmetic-logic unit adapted to perform a computer operation producing a result;at least one configuration input for configuring at least the computer operation performed by the at least one arithmetic-logic unit;at least one multiplexer located between at least one of the operand registers and the arithmetic-logic unit, the at least one of the operand registers adapted for feeding at least a first one of inputs of the multiplexer; andat least one feedback from the at least one result register to at least one input of the at least one multiplexer adapted for feeding result data back to the at least one arithmetic-logic unit; andis adapted for transmitting its output as at least one configuration code to the configuration input of at least one other of the at least some of the plurality of configurable elements via the interconnection;each of the at least one other of the at least some of the plurality of configurable elements:includes at least one configuration register adapted for storing therein during runtime the at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection; andis adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; andat least some of the configurable elements are adapted to process data according to their configuration. 119. The runtime configurable integrated data processing circuit according to claim 118, wherein the at least one arithmetic-logic unit of at least some of the at least some of the plurality of configurable elements comprises at least one of an adder and an ALU. 120. The runtime configurable integrated data processing circuit according to claim 118, wherein the at least one of the adder and the ALU includes a feed back channel for feeding back a result of the at least one of the adder and the ALU to an operand input of the at least one of the adder and the ALU via a multiplexer. 121. The runtime configurable integrated data processing circuit according to claim 117, wherein each of at least some of the at least some of the plurality of configurable elements comprises at least one respective configuration input for configuring the interconnection of the respective configurable elements to at least one other of the configurable elements. 122. The runtime configurable integrated data processing circuit according to any one of claims 119 and 121, wherein the runtime configurable integrated data processing circuit is a Field Programmable Gate Array Integrated Circuit (FPGA).
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