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Determining large-scale finite state machines using constraint relaxation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0610662 (2012-09-11)
등록번호 US-8903699 (2014-12-02)
발명자 / 주소
  • Vanspauwen, Niels
출원인 / 주소
  • Synopsys, Inc.
대리인 / 주소
    Fenwick & West LLP
인용정보 피인용 횟수 : 0  인용 특허 : 30

초록

A computer-implemented method of finite state machine using constraint relaxation. A first expression having a plurality of variables is accessed. A second expression is accessed that describes a constraint with respect to a first variable of the plurality of variables. At least one of the variables

대표청구항

1. A computer-implemented method for generating finite state machines comprising: accessing a first expression comprising a plurality of variables;accessing a second expression that describes a constraint with respect to a first variable of the plurality of variables of the first expression;eliminat

이 특허에 인용된 특허 (30)

  1. Apfelbaum, Larry; Savage, Peter L.; Bell, Katrin, Analyzing an extended finite state machine system model.
  2. Schwartz Edward L. ; Gormish Michael J., Apparatus and method for finite state machine coding of information selecting most probable state subintervals.
  3. Masuda Atsushi,JPX ; Sekine Masatoshi,JPX ; Hansen Jeffery P.,JPX, Apparatus and method for high-level synthesis of a logic circuit.
  4. Jay Christian Y.,FRX ; Poirot Franck J.,FRX, Automatic generation of test vectors for sequential circuits.
  5. Yu Tonny Kai Tong ; Chang Shir-Shen ; O'Neil Janet Lynn, Computer model of a finite state machine having inputs, outputs, delayed inputs and delayed outputs.
  6. Kanno Yuji (Tokyo JPX), Constructing method of finite-state machine performing transitions according to a partial type of success function and a.
  7. Vanspauwen, Niels, Determining large-scale finite state machines using constraint relaxation.
  8. Arcidiacono, Liliana; Matranga, Vincenzo, Fabrication method for a control unit for electronic microcontrollers or micoprocessors.
  9. Morse, Douglas C., Finite state machine with associated memory.
  10. Otsubo, Motohide, Function synthesizing method and apparatus, and recording medium on which program of said method is recorded.
  11. Vanspauwen, Niels, Large scale finite state machines.
  12. Iwashita Hiroaki,JPX ; Nakata Tsuneo,JPX, Logical device verification method and apparatus.
  13. Sun Xiao (Austin TX) Hull Carmie A. (Austin TX), Method and apparatus for constructing verification test sequences by merging and touring hierarchical unique input/outpu.
  14. Cheng Kwang-Ting (Santa Barbara CA) Krishnakumar Anjur S. (Rocky Hill NJ), Method and apparatus for determining the reachable states in a hybrid model state machine.
  15. Kita Ronald Allen ; Trumpler Mark Edward ; Elkind Lois Scirocco, Method and apparatus for generating an extended finite state machine architecture for a software specification.
  16. James Andrew Garrard Seawright, Method and apparatus for optimized partitioning of finite state machines synthesized from hierarchical high-level descriptions.
  17. Kita Ronald Allen ; Trumpler Mark Edward ; Elkind Lois Scirocco, Method and apparatus for testing implementations of software specifications.
  18. Steinz Hendrik Christian,NLX ; Dassel Johannes Roland,NLX, Method and device for processing signals in a protection system.
  19. Beer Ilan,ILX ; Eisner Cindy,ILX ; Rodeh Yoav,ILX, Method and system for reducing state space variables prior to symbolic model checking.
  20. Flora-Holmquist Alan Robert ; Morton Edward ; O'Grady James Day ; Staskauskas Mark Gerard, Method of and apparatus for constructing a complex control system and the complex control system created thereby.
  21. Wagner Ferdinand H. (24 Sterling Cir. ; Apt. 211 Wheaton IL 60187), Method of and apparatus for constructing a control system and control system created thereby.
  22. Giomi Jean-Charles, Method of extracting implicit sequential behavior from hardware description languages.
  23. Tamisier Thomas (St Germain en Laye FRX), Method of verification of a finite state sequential machine and resulting information support and verification tool.
  24. McElvain Kenneth S., Methods and apparatuses for automatic extraction of finite state machines.
  25. Petler Scott C., Minimizing logic by resolving "don't care" output values in a finite state machine.
  26. Herrera Ruben ; Sarpeshkar Rahul, Spike-triggered asynchronous finite state machine.
  27. Morley, Matthew John; Kashai, Yaron, System and method for compiling temporal expressions.
  28. Washabaugh Scott T. (Cary NC), System and method for designing a finite state machine to reduce power dissipation.
  29. Michael McNamara ; Chong Guan Tan ; Chiahon Chien ; David Todd Massey, System and method for identifying finite state machines and verifying circuit designs.
  30. Desai, Keyur B., Using and generating finite state machines to monitor system status.
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