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Ruthenium for a dielectric containing a lanthanide 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/31
  • H01L-029/51
  • H01L-021/28
출원번호 US-0052483 (2013-10-11)
등록번호 US-8907486 (2014-12-09)
발명자 / 주소
  • Ahn, Kie Y.
  • Forbes, Leonard
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman Lundberg & Woessner, P.A.
인용정보 피인용 횟수 : 3  인용 특허 : 326

초록

A gate containing ruthenium for a dielectric having an oxide containing a lanthanide and a method of fabricating such a combination gate and dielectric produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide gate may be formed on a lanthan

대표청구항

1. A method of forming an electronic device comprising: forming a dielectric in an integrated circuit, including forming an oxide region, the oxide region formed by one or more cycles of a monolayer or partial monolayer sequencing process, each of the one or more cycles including pulsing hydrogen in

이 특허에 인용된 특허 (326)

  1. Noble, Wendell P.; Forbes, Leonard; Ahn, Kie Y., 4 F2 folded bit line DRAM cell structure having buried bit and word lines.
  2. Wendell P. Noble ; Leonard Forbes ; Kie Y. Ahn, 4 F2 folded bit line dram cell structure having buried bit and word lines.
  3. Forbes Leonard ; Geusic Joseph E., Alternate method and structure for improved floating gate tunneling devices.
  4. Forbes Leonard ; Geusic Joseph E., Alternate method and structure for improved floating gate tunneling devices using textured surface.
  5. Ma Yanjun ; Ono Yoshi, Aluminum-doped zirconium dielectric film transistor structure and deposition method for same.
  6. Visokay, Mark R.; Colombo, Luigi; Rotondaro, Antonio L. P., Anneal sequence for high-κ film property optimization.
  7. Matijasevic, Vladimir; Kaplan, Todd, Apparatus and method for deposition of thin films.
  8. Sneh, Ofer; Seidel, Thomas E.; Galewski, Carl, Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition.
  9. Gadgil, Prasad Narhar, Apparatus for atomic layer chemical vapor deposition.
  10. Ahn, Kie Y.; Forbes, Leonard, Apparatus having a lanthanum-metal oxide semiconductor device.
  11. Bhattacharyya, Arup, Asymmetric band-gap engineered nonvolatile memory device.
  12. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed.
  13. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited Zr-Sn-Ti-O films.
  14. Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposited Zr-Sn-Ti-O films using TiI4.
  15. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited ZrAlOdielectric layers including ZrAlO.
  16. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited ZrTiOfilms.
  17. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited dielectric layers.
  18. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited lanthanide doped TiOx dielectric films.
  19. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited nanolaminates of HfO/ZrOfilms as gate dielectrics.
  20. Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics.
  21. Akram, Salman; Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection.
  22. Jang,Chuck; Dong,Zhong; Chan,Vei Han; Chen,Ching Hwa, Atomic layer deposition of interpoly oxides in a non-volatile memory device.
  23. Gates Stephen McConnell ; Neumayer Deborah Ann, Atomic layer deposition with nitrate containing precursors.
  24. Ahn,Kie Y.; Forbes,Leonard, Atomic layer-deposited LaAlO3 films for gate dielectrics.
  25. Ahn,Kie Y.; Forbes,Leonard, Atomic layer-deposited hafnium aluminum oxide.
  26. Ibok, Effiong; Zheng, Wei; Tripsas, Nicholas H.; Ramsbey, Mark T.; Cheung, Fred T K, Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer.
  27. Kori, Moris; Mak, Alfred W.; Byun, Jeong Soo; Lei, Lawrence Chung-Lai; Chung, Hua; Sinha, Ashok; Xi, Ming, Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques.
  28. Guenzer Charles S. (3852 Grove Ave. Palo Alto CA 94303), Bismuth titanate as a template layer for growth of crystallographically oriented silicon.
  29. Maiti Bikas ; Tobin Philip J. ; Mogab C. Joseph ; Hobbs Christopher ; Frisa Larry E.,DEX, CMOS semiconductor devices and method of formation.
  30. Eldridge, Jerome M., Capacitor dielectric having perovskite-type crystalline structure.
  31. Sang-don Nam KR; Jin-won Kim KR, Capacitor of semiconductor device.
  32. Ahn, Kie Y.; Forbes, Leonard, Capacitor structure forming methods.
  33. Vaartstra, Brian A., Chemical vapor deposition systems including metal complexes with chelating O- and/or N-donor ligands.
  34. Sandhu Gurtej S. ; Fazan Pierre, Chemical vapor deposition using organometallic precursors.
  35. Noble, Wendell P.; Forbes, Leonard, Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor.
  36. Leonard Forbes, Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device.
  37. Leonard Forbes, Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device.
  38. Leonard Forbes, Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device.
  39. Leonard Forbes, Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device.
  40. Forbes Leonard ; Geusic Joseph E. ; Ahn Kie Y., Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same.
  41. Barber, James R., Coil spring assembly.
  42. Ahn, Kie Y.; Forbes, Leonard, Composite dielectric forming methods and composite dielectrics.
  43. Raaijmakers, Ivo; Haukka, Suvi P.; Granneman, Ernst H. A., Conformal thin films over textured capacitor electrodes.
  44. Raaijmakers, Ivo; Haukka, Suvi P.; Granneman, Ernst H. A., Conformal thin films over textured capacitor electrodes.
  45. Bunshah Rointan F. (Playa del Rey CA) Deshpandey Chandra V. (Los Angeles CA) Doerr Hans J. (Westlake Village CA) Yoon Jong S. (Northridge CA), Controlled high rate deposition of metal oxide films.
  46. Ahn, Kie Y.; Forbes, Leonard, Copper technology for ULSI metallization.
  47. Ahn,Kie Y.; Forbes,Leonard, Crystalline or amorphous medium-K gate oxides, Y0and Gd0.
  48. Forbes, Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  49. Forbes, Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  50. Forbes,Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  51. Cabral, Jr.,Cyril; Callegari,Alessandro C.; Gribelyuk,Michael A.; Jamison,Paul C.; Lacey,Dianne L.; McFeely,Fenton R.; Narayanan,Vijay; Neumayer,Deborah A.; Ranade,Pushkar; Zafar,Sufi, Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures.
  52. Shinriki, Hiroshi; Homma, Koji, Device and method for processing substrate.
  53. Marsh, Eugene P., Devices containing platinum-iridium films and methods of preparing such films and devices.
  54. Uhlenbrock, Stefan; Marsh, Eugene P., Devices containing platinum-rhodium layers and methods.
  55. Marsh, Eugene P., Devices containing zirconium-platinum-containing materials and methods for preparing such materials and devices.
  56. Lee, Jongho; Lee, Nae-In, Dielectric layer for semiconductor device and method of manufacturing the same.
  57. Marsh,Eugene P., Dielectric material forming methods.
  58. Andreoni,Wanda; Curioni,Alessandro; Shevlin,Stephen A., Dielectric materials.
  59. Marsh Eugene P., Diffusion barrier layers and methods of forming same.
  60. Ahn, Kie; Forbes, Leonard, Doped aluminum oxide dielectrics.
  61. Ahn, Kie; Forbes, Leonard, Doped aluminum oxide dielectrics.
  62. Ma Yanjun ; Ono Yoshi, Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same.
  63. Nakamura Masayuki (Akishima JPX) Kawahara Takayuki (Hachiouji JPX) Kajigaya Kazuhiko (Iruma JPX) Oshima Kazuyoshi (Ohme JPX) Takahashi Tsugio (Ohme JPX) Otori Hiroshi (Ohme JPX) Matsumoto Tetsuro (Hi, Dynamic RAM and information processing system using the same.
  64. Fally Jacques,FRX, Dynamic distance and position sensor and method of measuring the distance and the position of a surface using a sensor.
  65. Ahn, Kie Y.; Forbes, Leonard, Electronic apparatus containing lanthanide yttrium aluminum oxide.
  66. Kashihara Keiichiro (Hyogo JPX) Okudaira Tomonori (Hyogo JPX) Itoh Hiromi (Hyogo JPX), Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer.
  67. Bojarczuk, Jr., Nestor A.; Cartier, Eduard A.; Guha, Supratik, Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique.
  68. Matthew S. Buynoski ; Paul R. Besser ; Paul L. King ; Eric N. Paton ; Qi Xiang, Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors.
  69. Ahn, Kiey Y.; Forbes, Leonard, Evaporated LaA1O3 films for gate dielectrics.
  70. Ahn, Kie Y.; Forbes, Leonard, Evaporation of Y-Si-O films for medium-K dielectrics.
  71. Ahn, Kie Y.; Forbes, Leonard, Evaporation of Y-Si-O films for medium-k dielectrics.
  72. Ahn, Kie Y.; Forbes, Leonard, Field emission display having porous silicon dioxide layer.
  73. Ahn, Kie Y.; Forbes, Leonard, Field emission display having reduced power requirements and method.
  74. Noble, Wendell P.; Forbes, Leonard, Field programmable logic arrays with vertical transistors.
  75. Wendell P. Noble ; Leonard Forbes, Field programmable logic arrays with vertical transistors.
  76. Forbes,Leonard; Eldridge,Jerome M., Flash memory with low tunnel barrier interpoly insulators.
  77. Yu, Bin; Wu, David, Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation.
  78. Ahn, Kie Y.; Forbes, Leonard, Formation of metal oxide gate dielectric.
  79. Kie Y. Ahn ; Leonard Forbes, Formation of metal oxide gate dielectric.
  80. Deacon Thomas E. ; Cheung David ; Lee Peter Wai-Man ; Huang Judy H., Gas distribution for CVD systems.
  81. Ni Tuqiang ; Demos Alex, Gas injection system for plasma processing.
  82. Ahn, Kie Y.; Forbes, Leonard, Gate oxides, and methods of forming.
  83. Forbes, Leonard; Eldridge, Jerome M., Graded composition gate insulators to reduce tunneling barriers in flash memory devices.
  84. Forbes, Leonard; Eldridge, Jerome M., Graded composition gate insulators to reduce tunneling barriers in flash memory devices.
  85. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Graded composition metal oxide tunnel barrier interpoly insulators.
  86. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Graded composition metal oxide tunnel barrier interpoly insulators.
  87. Werkhoven, Christiaan J.; Raaijmakers, Ivo; Haukka, Suvi P., Graded thin films.
  88. Wilk, Glen D.; Wallace, Robert M., Hafnium nitride gate dielectric.
  89. Ahn, Kie Y.; Forbes, Leonard, Hafnium tantalum oxide dielectrics.
  90. Ahn, Kie Y.; Forbes, Leonard, Hafnium tantalum titanium oxide films.
  91. Kaushik, Vidya S.; Nguyen, Bich-yen; Pietambaram, Srinivas V.; Schaeffer, III, James Kenyon, High K dielectric film.
  92. Minghwei Hong ; Ahmet Refik Kortan ; Jueinai Raynien Kwo ; Joseph Petrus Mannaerts, High dielectric constant gate oxides for silicon-based devices.
  93. Parsons, Gregory N.; Chambers, James J.; Kelly, M. Jason, High dielectric constant metal silicates formed by controlled metal-surface reactions.
  94. Ahn, Kie Y.; Forbes, Leonard, High-quality praseodymium gate dielectrics.
  95. Ahn,Kie Y.; Forbes,Leonard, Highly reliable amorphous high-k gate dielectric ZrON.
  96. Ahn, Kie Y.; Forbes, Leonard, Highly reliable amorphous high-k gate dielectric ZrOXNY.
  97. Ahn,Kie Y.; Forbes,Leonard, Highly reliable amorphous high-k gate oxide ZrO2.
  98. Ahn, Kie Y.; Forbes, Leonard, Highly reliable gate oxide and method of fabrication.
  99. Lee Seaung Suk,KRX ; Kim Ho Gi,KRX ; Kim Jong Choul,KRX ; Choi Soo Han,KRX, Hot-wall CVD method for forming a ferroelectric film.
  100. Yoon, Dong-Soo, Hydrogen barrier layer and method for fabricating semiconductor device having the same.
  101. Yoshikawa, Takamasa; Satoh, Hideo; Yoshizawa, Atsushi; Yamada, Takashi; Chuman, Takashi; Negishi, Nobuyasu; Iwasaki, Shingo; Sakemura, Kazuto; Hata, Takuya; Ogasawara, Kiyohide, Image pickup device including electron-emitting devices.
  102. Forbes,Leonard, In service programmable logic arrays with low tunnel barrier interpoly insulators.
  103. Forbes Leonard ; Geusic Joseph E., Information handling system having improved floating gate tunneling devices.
  104. Sarigiannis, Demetrius; Meng, Shuang; Derderian, Garo J., Insitu post atomic layer deposition destruction of active species.
  105. Moise Theodore S. ; Xing Guoqiang ; Visokay Mark ; Gaynor Justin F. ; Gilbert Stephen R. ; Celii Francis ; Summerfelt Scott R. ; Colombo Luigi, Integrated circuit and method.
  106. Forbes, Leonard; Eldridge, Jerome M.; Ahn, Kie Y., Integrated circuit memory device and method.
  107. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same.
  108. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same.
  109. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same.
  110. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.
  111. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.
  112. Ahn, Kie Y.; Forbes, Leonard, Integrated decoupling capacitors.
  113. Arne W. Ballantine ; Douglas A. Buchanan ; Eduard A. Cartier ; Kevin K. Chan ; Matthew W. Copel ; Christopher P. D'Emic ; Evgeni P. Gousev ; Fenton Read McFeely ; Joseph S. Newbury ; Harald , Interfacial oxidation process for high-k gate dielectric process integration.
  114. Ahn,Kie Y.; Forbes,Leonard, Lanthanide doped TiOdielectric films.
  115. Ahn,Kie Y.; Forbes,Leonard, Lanthanide doped TiOdielectric films by plasma oxidation.
  116. Ahn, Kie Y.; Forbes, Leonard, Lanthanide doped TiOx dielectric films.
  117. Ahn, Kie Y.; Forbes, Leonard, Lanthanide doped TiOx dielectric films by plasma oxidation.
  118. Ahn,Kie Y.; Forbes,Leonard, Lanthanide oxide / hafnium oxide dielectric layers.
  119. Ahn,Kie Y.; Forbes,Leonard, Lanthanide oxide / hafnium oxide dielectrics.
  120. Ahn,Kie Y.; Forbes,Leonard, Lanthanide oxide dielectric layer.
  121. Ahn,Kie Y.; Forbes,Leonard, Lanthanide oxide/hafnium oxide dielectrics.
  122. Ahn,Kie; Forbes,Leonard, Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics.
  123. Glassman Timothy E. (Danbury CT) Chayka Paul V. (New Milford CT), Lanthanide/phosphorus precursor compositions for MOCVD of lanthanide/phosphorus oxide films.
  124. Ahn,Kie Y.; Forbes,Leonard, Lanthanum hafnium oxide dielectrics.
  125. Maria, Jon-Paul; Kingon, Angus Ian, Lanthanum oxide-based dielectrics for integrated circuit capacitors.
  126. Maria, Jon-Paul; Kingon, Angus Ian, Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors.
  127. Frankel Jonathan ; Shmurun Inna ; Sivaramakrishnan Visweswaren ; Fukshansky Eugene, Lid assembly for high temperature processing chamber.
  128. Bin Yu, Low temperature process to locally form high-k gate dielectrics.
  129. Joseph E. Geusic, Low temperature silicon wafer bond process with bulk material bond strength.
  130. Ahn, Kie Y.; Forbes, Leonard, Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics.
  131. Ahn, Kie Y.; Forbes, Leonard, Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics.
  132. Ahn, Kie Y.; Forbes, Leonard, Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics.
  133. Ahn,Kie Y.; Forbes,Leonard, Low-temperature growth high-quality ultra-thin praseodymium gate dieletrics.
  134. Cho, Hag-ju, METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES THAT INCLUDE A METAL OXIDE LAYER DISPOSED ON ANOTHER LAYER TO PROTECT THE OTHER LAYER FROM DIFFUSION OF IMPURITIES AND INTEGRATED CIRCUIT DEVICES M.
  135. Hsu, Sheng Teng; Zhang, Fengyan; Li, Tingkai, MFOS memory transistor & method of fabricating same.
  136. Yu, Bin; Xiang, Qi, MOSFET device having high-K dielectric layer.
  137. Yu, Bin; Paton, Eric N., MOSFET having a double gate.
  138. Yu, Bin; Xiang, Qi; Karlsson, Olov; Wang, HaiHong; Krivokapic, Zoran, MOSFETs with differing gate dielectrics and method of formation.
  139. Wang, Xingwu; Helfer, Jeffrey L.; MacDonald, Stuart G., Magnetically shielded assembly.
  140. Forbes Leonard ; Noble Wendell P., Memory address decode array with vertical transistors.
  141. Leonard Forbes ; Wendell P. Noble, Memory address decode array with vertical transistors.
  142. Doyle Patrick F. (Hillsboro OR) Cross Leonard W. (Beaverton OR) Noar Roger (Tigard OR), Memory address decoder with storage for memory attribute information.
  143. Noble, Wendell P.; Forbes, Leonard; Ahn, Kie Y., Memory cell having a vertical transistor with buried source/drain and dual gates.
  144. Wendell P. Noble ; Leonard Forbes ; Kie Y. Ahn, Memory cell having a vertical transistor with buried source/drain and dual gates.
  145. Forbes Leonard ; Noble Wendell P. ; Ahn Kie Y., Memory cell with vertical transistor and buried word and body lines.
  146. Leonard Forbes ; Wendell P. Noble ; Kie Y. Ahn, Memory cell with vertical transistor and buried word and body lines.
  147. Poplingher Mircea ; Chen Wenliang ; Suryanarayanan Ganesh ; Chen Wayne W. ; Lo Roger Y., Memory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycle.
  148. Aronowitz,Sheldon; Zubkov,Vladimir; Sun,Grace S., Memory device having an electron trapping layer in a high-K dielectric gate stack.
  149. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide nanolaminates.
  150. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide-conductor nanolaminates.
  151. Hentges, Patrick J.; Greene, Laura H.; Pafford, Margaret Mary; Westwood, Glenn; Klemperer, Walter G., Metal alkoxides and methods of making same.
  152. Kirlin Peter S. ; Brown Duncan W. ; Baum Thomas H. ; Vaarstra Brian A. ; Gardiner Robin A., Metal complex source reagents for chemical vapor deposition.
  153. Brian A. Vaartstra, Metal complexes with chelating O-and/or N-donor ligands.
  154. Sam Yang ; Vishnu K. Agarwal, Metal oxynitride capacitor barrier layer.
  155. Forbes,Leonard; Farrar,Paul A.; Ahn,Kie Y., Metal-substituted transistor gates.
  156. Ahn, Kie Y.; Forbes, Leonard, Method and apparatus for the fabrication of ferroelectric films.
  157. Kie Y. Ahn ; Leonard Forbes, Method and apparatus for the fabrication of ferroelectric films.
  158. Geusic, Joseph E.; Forbes, Leonard; Ahn, Kie Y., Method and structure for high capacitance memory cells.
  159. Geusic, Joseph E.; Forbes, Leonard; Ahn, Kie Y., Method and structure for high capacitance memory cells.
  160. Gardner Mark I. ; Nistler John L. ; May Charles E., Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices.
  161. Basceri, Cem; Gealy, Dan; Sandhu, Gurtej S., Method for controlling deposition of dielectric films.
  162. Farrar,Paul A.; Eldridge,Jerome M., Method for controlling diffusion in semiconductor regions.
  163. Conley, Jr., John F.; Ono, Yoshi; Solanki, Rajendra, Method for depositing a nanolaminate film by atomic layer deposition.
  164. Ramdani, Jamal; Droopad, Ravindranath; Yu, Zhiyi, Method for fabricating a semiconductor structure including a metal oxide interface with silicon.
  165. Eugene P. Marsh, Method for fabricating an SrRuO3 film.
  166. Kim, Younsoo, Method for fabricating metal electrode with atomic layer deposition (ALD) in semiconductor device.
  167. Kubota,Masafumi; Hayashi,Shigenori, Method for fabricating semiconductor device.
  168. Messing, Gary L.; Kwon, Songtae; Sabolsky, Edward M., Method for fabrication of lead-based perovskite materials.
  169. Tarui Yasuo (No. 6-4 ; Minamisawa 5-chome Higashikurume City ; Tokyo JPX) Soutome Yoshihiro (Osaka JPX) Morita Shinichi (Yokosuka JPX) Tanimoto Satoshi (Tokyo JPX), Method for ferroelectric thin film production.
  170. Choi, Sung-Je, Method for forming a dielectric layer of a semiconductor device.
  171. Jeon, Joong S; Zhong, Huicai, Method for forming a field effect transistor having a high-k gate dielectric and related structure.
  172. Forbes, Leonard, Method for forming a programmable decoder with vertical transistors.
  173. Geusic Joseph E. ; Forbes Leonard ; Ahn Kie Y., Method for forming high capacitance memory cells.
  174. Maiti Bikas ; Tobin Philip J. ; Hegde Rama I. ; Cuellar Jesus, Method for forming high dielectric constant metal oxides.
  175. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer.
  176. Choi, Eun-Seok, Method for forming metal films.
  177. Yun-sook Chae KR; Sang-bom Kang KR; Gil-heyun Choi KR; In-sang Jeon KR, Method for forming metal layer of semiconductor device using metal halide gas.
  178. Kang Sang-bom,KRX ; Chae Yun-sook,KRX ; Park Chang-soo,KRX ; Lee Sang-in,KRX, Method for forming metal layer using atomic layer deposition.
  179. Vaartstra Brian A., Method for forming metal-containing films using metal complexes with chelating O- and/or N-donor ligands.
  180. Yano Yoshihiko,JPX ; Noguchi Takao,JPX ; Nagano Katsuto,JPX, Method for forming oxide thin film and the treatment of silicon substrate.
  181. Cho, Ho Jin, Method for forming polyatomic layers.
  182. Ahn, Kie Y.; Forbes, Leonard, Method for forming single electron resistor memory.
  183. Ritala, Mikko; Rahtu, Antti; Leskela, Markku; Kukli, Kaupo, Method for growing thin oxide films.
  184. Ruff, Alexander; Kegel, Wilhelm; Karcher, Wolfram; Schrems, Martin, Method for increasing the capacitance in a storage trench.
  185. Ahn, Kie Y.; Forbes, Leonard, Method for making a ferroelectric memory transistor.
  186. Christopher C. Hobbs ; Baohong Cheng ; Lurae G. Dip, Method for making semiconductor device.
  187. Iwaki,Takashi; Tsukamoto,Takeo, Method for manufacturing carbon fibers and electron emitting device using the same.
  188. Tatsuro Maeda JP, Method for manufacturing self-matching transistor.
  189. Suntola Tuomo S. (Espoo FIX) Pakkala Arto J. (Espoo FIX) Lindfors Sven G. (Espoo FIX), Method for performing growth of compound thin films.
  190. Soininen Erkki (Espoo FIX) Leppnen Marja (Espoo FIX), Method for preparing a multilayer structure for electroluminescent components.
  191. Suntola Tuomo (Riihikallio 02610 Espoo 61 SF) Antson Jorma (Urheilutie 22 ; 01350 Vantaa 35 SF), Method for producing compound thin films.
  192. Eugene P. Marsh, Method for producing low carbon/oxygen conductive layers.
  193. Eugene P. Marsh, Method for producing low carbon/oxygen conductive layers.
  194. Van Wijck, Margreet Albertine Anne-Marie, Method for vapour deposition of a film onto a substrate.
  195. Ahn,Kie Y.; Forbes,Leonard, Method including forming gate dielectrics having multiple lanthanide oxide layers.
  196. Brian A. Vaartstra, Method of depositing films by using carboxylate complexes.
  197. Vaartstra Brian A., Method of depositing films by using carboxylate complexes.
  198. Vaartstra Brian A., Method of depositing films on semiconductor devices by using carboxylate complexes.
  199. Ko, Chang Hyun; You, Young Sub; Lee, Jai Dong; Hwang, Ki Hyun, Method of fabricating a capacitor of a semiconductor device.
  200. Ahn, Kie Y.; Forbes, Leonard, Method of fabricating a highly reliable gate oxide.
  201. Leonard Forbes ; Kie Y. Ahn, Method of fabricating a semiconductor-on-insulator memory cell with buried word and body lines.
  202. Marsh, Eugene P., Method of fabricating an SrRuO3 film.
  203. Krivokapic, Zoran, Method of fabricating an ultra-thin fully depleted SOI device with T-shaped gate.
  204. Hidehiko, Shiraiwa; Halliyal, Arvind; Park, Jaeyong, Method of formation of semiconductor resistant to hot carrier injection stress.
  205. Ma Yanjun ; Ono Yoshi, Method of forming a doped metal oxide dielectric film.
  206. Batra,Shubneesh; Sandhu,Gurtej, Method of forming a non-volatile electron storage memory and the resulting device.
  207. Forbes, Leonard; Ahn, Kie Y., Method of forming a weak ferroelectric transistor.
  208. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Method of forming an optical fiber interconnect through a semiconductor wafer.
  209. Gardiner Robin A. ; Kirlin Peter S. ; Baum Thomas H. ; Gordon Douglas ; Glassman Timothy E. ; Pombrik Sofia ; Vaartstra Brian A., Method of forming metal films on a substrate by chemical vapor deposition.
  210. Pekka J. Soininen FI; Kai-Erik Elers FI; Suvi Haukka FI, Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH.
  211. Ahn, Kie Y.; Forbes, Leonard, Method of making a chip packaging device having an interposer.
  212. Ahn, Kie Y.; Forbes, Leonard, Method of manufacturing a single electron resistor memory device.
  213. Min,Yo sep; Bae,Eun ju; Choi,Won bong; Cho,Young jin; Lee,Jung hyun, Method of manufacturing inorganic nanotube.
  214. Arima Hideaki (Hyogo JPX), Method of manufacturing semiconductor memory device.
  215. Elers, Kai-Erik, Method of modifying source chemicals in an ald process.
  216. Yamagata, Kenji, Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device.
  217. Conley, Jr., John F.; Ono, Yoshi; Solanki, Rajendra, Method to deposit a stacked high-κ gate dielectric for CMOS applications.
  218. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  219. Ellie Yieh ; Li-Qun Xia ; Srinivas Nemani, Methods and apparatus for shallow trench isolation.
  220. Ahn,Kie Y.; Forbes,Leonard, Methods for atomic-layer deposition of aluminum oxides in integrated circuits.
  221. Agarwal, Vishnu K.; Derderian, Garo; Sandhu, Gurtej S.; Li, Weimin M.; Visokay, Mark; Basceri, Cem; Yang, Sam, Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers.
  222. Basceri, Cem; Sandhu, Gurtej, Methods for forming conductive structures and structures regarding same.
  223. Vaartstra Brian A., Methods for forming conformal iridium layers on substrates.
  224. Ahn, Kie Y.; Forbes, Leonard, Methods for forming dielectric materials and methods for forming semiconductor devices.
  225. Brian A. Vaartstra, Methods for forming iridium and platinum containing films on substrates.
  226. Alessandro Cesare Callegari ; Fuad Elias Doany ; Evgeni Petrovich Gousev ; Theodore Harold Zabel, Methods for forming metal oxide layers with enhanced purity.
  227. Haukka, Suvi P.; Tuominen, Marko, Methods for making a dielectric stack in an integrated circuit.
  228. Eldridge, Jerome M., Methods of forming perovskite-type material and capacitor dielectric having perovskite-type crystalline structure.
  229. Ahn, Kie Y.; Forbes, Leonard, Methods of forming titanium silicon oxide.
  230. Yoshi Ono ; Wei-Wei Zhuang ; Rajendra Solanki, Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate.
  231. Liang Gi Yao TW; Ming Fang Wang TW; Shih Chang Chen TW; Mong Song Liang TW, Methods to create high-k dielectric gate electrodes with backside cleaning.
  232. Ahn, Kie Y., Methods, systems, and apparatus for uniform chemical-vapor depositions.
  233. Lee, Kang N., Multilayer article characterized by low coefficient of thermal expansion outer layer.
  234. Yanjun Ma ; Yoshi Ono, Multilayer dielectric stack and method.
  235. Senzaki, Yoshihide, Multilayer high κ dielectric films.
  236. Yano Yoshihiko,JPX ; Noguchi Takao,JPX, Multilayer thin film, substrate for electronic device, electronic device, and preparation of multilayer oxide thin film.
  237. Forbes, Leonard, Multilevel semiconductor-on-insulator structures and circuits.
  238. Forbes, Leonard, Nanocrystal write once read only memory for archival storage.
  239. Arvind Halliyal ; Robert Bertram Ogle, Jr. ; Joong S. Jeon ; Fred Cheung ; Effiong Ibok, Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material.
  240. Jin, Been-Yih; Arghavani, Reza; Chau, Robert, Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors.
  241. Hoefler, Alexander B.; Chindalore, Gowrishankar L.; Ingersoll, Paul A.; Swift, Craig T., Non-volatile memory device having an anti-punch through (APT) region.
  242. Arami Junichi,JPX ; Ishikawa Kenji,JPX ; Kitamura Masayuki,JPX, One-by-one type heat-processing apparatus.
  243. Yano Yoshihiko,JPX ; Noguchi Takao,JPX, Oxide thin film, electronic device substrate and electronic device.
  244. Yang, Sam; Zheng, Lingyi A., Oxygen barrier for cell container process.
  245. Suen, Chi Ming, Paraffin wax warmer bath.
  246. Cain John L. (Schertz TX) Relue Michael P. (San Antonio TX) Costabile Michael E. (San Antonio TX) Marsh William P. (San Antonio TX), Plasma processing apparatus.
  247. Tei, Goushu; Tanaka, Nobuyoshi; Ohmi, Tadahiro; Hirayama, Masaki, Plasma treatment method and method of manufacturing optical parts using the same.
  248. Nakahigashi Takahiro (Kyoto JPX) Murakami Hiroshi (Kyoto JPX) Otani Satoshi (Osaka JPX) Tabata Takao (Kyoto JPX) Maeda Hiroshi (Kyoto JPX) Kirimura Hiroya (Kyoto JPX) Kuwahara Hajime (Kyoto JPX), Plasma-CVD method and apparatus.
  249. Ahn Kie Y. ; Forbes Leonard, Porous silicon oxycarbide integrated circuit insulator.
  250. Ahn, Kie Y.; Forbes, Leonard, Porous silicon oxycarbide integrated circuit insulator.
  251. Kie Y. Ahn ; Leonard Forbes, Porous silicon oxycarbide integrated circuit insulator.
  252. Bruley, John; Cabral, Jr., Cyril; Lavoie, Christian; Wagner, Tina J.; Wang, Yun Yu; Wildman, Horati S.; Hon, Wong Kwong, Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi.
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  256. Jeon, Joong, Preparation of composite high-K dielectrics.
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  260. Yoshihiko Yano JP; Takao Noguchi JP, Process for preparing ferroelectric thin films.
  261. Putkonen, Matti, Process for producing oxide thin films.
  262. Wilk, Glen David; Ye, Peide, Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate.
  263. Kamikawa Yuuji (Uto JPX) Matsumura Kimiharu (Kumamoto JPX) Nomura Masafumi (Kumamoto JPX) Nagata Junichi (Kumamoto JPX), Processing apparatus with a gas distributor having back and forth parallel movement relative to a workpiece support surf.
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  265. Forbes,Leonard; Eldridge,Jerome M.; Ahn,Kie Y., Programmable array logic or memory devices with asymmetrical tunnel barriers.
  266. Noble, Wendell P.; Forbes, Leonard, Programmable logic array with vertical transistors.
  267. Wendell P. Noble ; Leonard Forbes, Programmable logic array with vertical transistors.
  268. Forbes,Leonard, Programmable memory address and decode circuits with low tunnel barrier interpoly insulators.
  269. Forbes,Leonard, Programmable memory address and decode circuits with low tunnel barrier interpoly insulators.
  270. Forbes, Leonard, Programmable memory address and decode circuits with ultra thin vertical body transistors.
  271. Forbes, Leonard, Programmable memory address and decode circuits with vertical body transistors.
  272. Forbes Leonard ; Noble Wendell P., Programmable memory address decode array with vertical transistors.
  273. Forbes, Leonard; Noble, Wendell P., Programmable memory address decode array with vertical transistors.
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  276. Sneh Ofer, Radical-assisted sequential CVD.
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  278. Ahn, Kie Y.; Forbes, Leonard, Ruthenium for a dielectric containing a lanthanide.
  279. Krivokapic, Zoran; Xiang, Qi; Yu, Bin, SOI device with metal source/drain and method of fabrication.
  280. Rajeevakumar Thekkemadathil V. (Scarsdale NY), SOI trench DRAM cell for 256 MB DRAM and beyond.
  281. Jeong Hee Oh KR, SOI wafer device and a method of fabricating the same.
  282. Forbes, Leonard, SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  283. Bhattacharyya,Arup, Scalable flash/NV structures and devices with extended endurance.
  284. Forbes,Leonard; Ahn,Kie Y., Self aligned metal gates on high-k dielectrics.
  285. Forbes,Leonard; Ahn,Kie Y., Self aligned metal gates on high-k dielectrics.
  286. Hirano, Izumi; Koyama, Masato; Nishiyama, Akira, Semiconductor device and method of manufacturing the same.
  287. Tsunashima, Yoshitaka; Inumiya, Seiji; Suizu, Yasumasa; Ozawa, Yoshio; Miyano, Kiyotaka; Tanaka, Masayuki, Semiconductor device having a gate insulating film structure including an insulating film containing metal, silicon and oxygen and manufacturing method thereof.
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  289. Kutsunai, Toshie; Hayashi, Shinichiro; Mikawa, Takumi; Judai, Yuji, Semiconductor device with oxygen diffusion barrier layer termed from composite nitride.
  290. Teraguchi Nobuaki,JPX, Semiconductor light-emitting device.
  291. Gary M. Moore ; Katsuhito Nishikawa, Semiconductor processing reactor controllable gas jet assembly.
  292. Jamal Ramdani ; Ravindranath Droopad ; Lyndee L. Hilt ; Kurt William Eisenbeiser, Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same.
  293. Morishita, Takashi; Matsui, Masahiro, Semiconductor substrate and its production method, semiconductor device comprising the same and its production method.
  294. Kalal, Peter J.; Quesada, Mark A., Sensors, methods of manufacture and sensing methods.
  295. Sherman Arthur, Sequential chemical vapor deposition.
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  297. Li, Weimin, Sequential pulse deposition.
  298. Forbes,Leonard, Service programmable logic arrays with low tunnel barrier interpoly insulators.
  299. Forbes,Leonard, Service programmable logic arrays with low tunnel barrier interpoly insulators.
  300. Ahn Kie Y. ; Forbes Leonard, Silicon multi-chip module packaging with integrated passive components and method of making.
  301. Fengyan Zhang ; Yanjun Ma ; Jer-Shen Maa ; Wei-Wei Zhuang ; Sheng Teng Hsu, Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same.
  302. Ahn Kie ; Forbes Leonard, Single electron MOSFET memory device and method.
  303. Ahn Kie Y. ; Forbes Leonard, Single electron resistor memory device and method for use thereof.
  304. Hsu, Sheng Teng; Zhang, Fengyan, Single transistor ferroelectric transistor structure with high-K insulator and method of fabricating same.
  305. Ahn Kie Y. ; Forbes Leonard ; Cloud Eugene H., Structure and method for a high performance electronic packaging assembly.
  306. Ahn, Kie Y.; Forbes, Leonard; Cloud, Eugene H., Structure and method for a high-performance electronic packaging assembly.
  307. Ahn Kie Y. ; Forbes Leonard, Structure and method for dual gate oxide thicknesses.
  308. Ahn, Kie Y.; Forbes, Leonard, Structure and method for dual gate oxide thicknesses.
  309. Ahn, Kie Y.; Forbes, Leonard, Structure and method for dual gate oxide thicknesses.
  310. Ahn, Kie Y.; Forbes, Leonard, Structure and method for dual gate oxide thicknesses.
  311. Marsh Eugene P., Structures including low carbon/oxygen conductive layers.
  312. Ahn, Kie Y.; Forbes, Leonard, Structures, methods, and systems for ferroelectric memory transistors.
  313. Ahn, Kie Y.; Forbes, Leonard, Structures, methods, and systems for ferroelectric memory transistors.
  314. Pomarede, Christophe F.; Roberts, Jeff; Shero, Eric J., Surface preparation prior to deposition.
  315. Bakli, Mouloud; Ghanayem, Steve G.; Tran, Huyen T., Tantalum nitride CVD deposition by tantalum oxide densification.
  316. Eppich,Denise M.; Weimer,Ronald A., Transistor devices, and methods of forming transistor devices and circuit devices.
  317. Zoran Krivokapic, Ultra-thin fully depleted SOI device with T-shaped gate and method of fabrication.
  318. Klemperer, Walter G.; Lee, Jason; Mikalsen, Erik A.; Payne, David A., Ultrathin oxide films on semiconductors.
  319. Wang, Zhigang; Guo, Xin; He, Yue-Song, Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling.
  320. Halliyal, Arvind; Ramsbey, Mark T.; Zhang, Wei; Randolph, Mark W.; Cheung, Fred T. K., Use of high-K dielectric material in modified ONO structure for semiconductor devices.
  321. Halliyal, Arvind; Ramsbey, Mark T.; Chang, Kuo-Tung; Tripsas, Nicholas H.; Ogle, Robert B., Use of high-k dielectric materials in modified ONO structure for semiconductor devices.
  322. Ohashi Tadashi,JPX ; Chaki Katuhiro,JPX ; Xin Ping,JPX ; Fujii Tatsuo,JPX ; Iwata Katsuyuki,JPX ; Mitani Shinichi,JPX ; Honda Takaaki,JPX, Vapor deposition apparatus and method for forming thin film.
  323. Forbes Leonard, Vertical bipolar read access for low voltage memory cell.
  324. Forbes, Leonard, Write once read only memory employing charge trapping in insulators.
  325. Wallace Robert M. ; Stoltz Richard A. ; Wilk Glen D., Zirconium and/or hafnium silicon-oxynitride gate dielectric.
  326. Ahn, Kie Y.; Forbes, Leonard, Zirconium-doped tantalum oxide films.

이 특허를 인용한 특허 (3)

  1. Ahn, Kie Y.; Forbes, Leonard, Gallium lanthanide oxide films.
  2. Ahn, Kie Y.; Forbes, Leonard, Gallium lathanide oxide films.
  3. Gealy, F. Daniel; Bhat, Vishwanath; Srividya, Cancheepuram V.; Rocklein, M. Noel, Graded dielectric structures.
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