Unified bus architecture for PoE communication and control
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-001/26
G06F-013/00
H04L-012/10
출원번호
US-0538424
(2012-06-29)
등록번호
US-8909953
(2014-12-09)
발명자
/ 주소
Diab, Wael William
출원인 / 주소
Broadcom Corporation
대리인 / 주소
Sterne, Kessler, Goldstein & Fox P.L.L.C.
인용정보
피인용 횟수 :
0인용 특허 :
18
초록▼
Embodiments of a unified communication and control bus architecture for Ethernet and/or PoE systems are provided. Embodiments enable a unified communication and control bus architecture that significantly simplifies communication and control in Ethernet and/or PoE systems. Embodiments enable signifi
Embodiments of a unified communication and control bus architecture for Ethernet and/or PoE systems are provided. Embodiments enable a unified communication and control bus architecture that significantly simplifies communication and control in Ethernet and/or PoE systems. Embodiments enable significant savings both in terms of cost and complexity as the number of communication and control buses is reduced down to one. Embodiments can be used in various Ethernet and/or PoE implementations, including, for example, single PCB-single PoE, single PCB-multiple PoE, chassis-based switch, and stackable-based switch configurations. Further, embodiments can be implemented using standard Ethernet as well as proprietary implementations.
대표청구항▼
1. A switch, comprising: a supervisory slot, including a controller;a first linecard slot, including a first Power Over Ethernet (PoE) linecard;a second linecard slot, including a second PoE linecard; anda shared communication and control bus configured to couple the supervisory slot to each of the
1. A switch, comprising: a supervisory slot, including a controller;a first linecard slot, including a first Power Over Ethernet (PoE) linecard;a second linecard slot, including a second PoE linecard; anda shared communication and control bus configured to couple the supervisory slot to each of the first and second linecard slots,wherein at least one of the first and second linecard slots comprises: re-referencing circuitry configured to re-reference an output of the controller from a first logic environment of the controller to a second logic environment. 2. The switch of claim 1, wherein at least one of the first and second PoE linecards includes a transceiver physical layer device (PHY) and a PoE subsystem. 3. The switch of claim 2, wherein the PoE subsystem includes at least one of a DC power supply and a Power Source Equipment (PSE) controller. 4. The switch of claim 1, wherein the supervisory slot further includes an isolation device, the isolation device configured to isolate the controller from at least one of the first and second PoE linecards. 5. The switch of claim 1, wherein the second logic environment corresponds to a logic environment of a transceiver physical layer device (PHY) of said at least one of the first and second linecard slots. 6. The switch of claim 5, wherein said at least one of the first and second linecard slots further comprises: an isolation device configured to isolate said re-referencing circuitry from PoE subsystem of said at least one of the first and second linecard slots. 7. The switch of claim 1, wherein the second logic environment corresponds to a logic environment of a PoE subsystem of said at least one of the first and second linecard slots. 8. The switch of claim 7, wherein said at least one of the first and second linecard slots further comprises: an isolation device configured to isolate said re-referencing circuitry from a transceiver physical layer device (PHY) of said at least one of the first and second linecard slots. 9. The switch of claim 1, wherein said at least one of the first and second linecard slots further comprises: a bus controller, coupled between the re-referencing circuitry and a PoE linecard of said at least one of the first and second linecard slots. 10. The switch of claim 1, wherein the shared communication and control bus implements a shared access protocol. 11. The switch of claim 1, wherein the shared communication and control bus implements Carrier Sense Multiple Access / Collision Detection (CSMA/CD). 12. The switch of claim 1, wherein the shared communication and control bus implements a token-based shared access protocol. 13. The switch of claim 1, wherein the shared communication and control bus is a multi-drop bus, and wherein each of the supervisory slot, the first linecard slot, and the second linecard slot is attached to the bus via a respective tap point. 14. A switch, comprising: a supervisory slot, including a controller;a linecard slot, including a Power Over Ethernet (PoE) linecard and a bus controller, the PoE linecard including a Power Source Equipment (PSE) controller and PoE power circuitry; anda communication and control bus configured to couple the supervisory slot to the linecard slot via the bus controller,wherein the controller is configured to send a command over the communication and control bus, and wherein the bus controller is configured to receive the command over the communication and control bus and to forward the command to the PoE linecard when the command is addressed to the PoE linecard. 15. The switch of claim 14, wherein the PoE linecard further comprises a transceiver physical layer device (PHY). 16. The switch of claim 15, wherein the PoE linecard further comprises an isolation device coupled in a path between the PSE controller and the bus controller. 17. A switch, comprising: a supervisory slot, including a controller;a linecard slot, including a Power Over Ethernet (PoE) linecard; anda communication and control bus configured to couple the supervisory slot to the linecard slot,wherein the PoE linecard includes a transceiver physical layer device (PHY) and a Power Source Equipment (PSE) subsystem, andwherein the linecard slot further comprises: a first bus controller configured to couple the PHY of the PoE linecard to a first tap point of the communication and control bus; anda second bus controller configured to couple the PSE subsystem of the PoE linecard to a second tap point of the communication and control bus. 18. The switch of claim 17, wherein the linecard slot further comprises an isolation device coupled between the second bus controller and the second tap point of the communication and control bus. 19. The switch of claim 17, wherein the PSE subsystem includes at least one of a DC power supply and a PSE controller.
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이 특허에 인용된 특허 (18)
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