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Apparatus and method for precluding execution of certain instructions in a secure execution mode microprocessor

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-021/00
  • G06F-021/72
  • G06F-021/70
출원번호 US-0263263 (2008-10-31)
등록번호 US-8910276 (2014-12-09)
발명자 / 주소
  • Henry, G. Glenn
  • Parks, Terry
출원인 / 주소
  • Via Technologies, Inc.
대리인 / 주소
    Huffman, Richard K.
인용정보 피인용 횟수 : 0  인용 특허 : 69

초록

An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs ar

대표청구항

1. An apparatus providing for a secure execution environment, comprising: a microprocessor, comprising: one or more execution units, configured to execute non-secure application programs and a secure application program, wherein said non-secure application programs are accessed from a system memory

이 특허에 인용된 특허 (69)

  1. Watt,Simon Charles, Apparatus and method for controlling access to a memory unit.
  2. Johnson,Anders, Apparatus and method for secure filed upgradability with hard wired public key.
  3. Johnson, Richard C.; Morgan, Andrew; Anvin, H. Peter; Torvalds, Linus, Architecture, system, and method for operating on encrypted and/or hidden information.
  4. Mazzagatte, Craig; Slick, Royce E.; Iwamoto, Neil, Authenticated secure printing.
  5. Arnold, Mark G.; Winkel, Mark D., Computer systems to inhibit unauthorized copying, unauthorized usage, and automated cracking of protected software.
  6. Kaplan, Michael M.; Ober, Timothy; Reed, Peter; Doud, Robert W., Cryptographic co-processor.
  7. Takahashi Richard J. (Phoenix AZ), Dual purpose security architecture with protected internal operating system.
  8. Hall Christopher M. (Redwood City CA), EPROM register providing a full time static output signal.
  9. Shankar, Narendar; Paksoy, Erdal; Vanyo, Todd, Encrypted and other keys in public and private battery memories.
  10. Henry G. Glenn ; Martin-de-Nicolas Arturo ; Miner Daniel G., Fuse array control for smart function enable.
  11. Goss, Steven C., Hybrid cryptographic accelerator and method of operation thereof.
  12. Curiger Andreas ; Little Wendell L., Integrated circuit having hardware circuitry to prevent electrical or thermal stressing of the silicon circuitry.
  13. Sibigtroth James M. (Round Rock TX) Rhoades Michael W. (Austin TX) Grimmer ; Jr. George G. (Austin TX) Longwell Susan W. (Austin TX), Integrated circuit microcontroller with on-chip memory and external bus interface and programmable mechanism for securin.
  14. Goss, Steven; Conti, Gregory, Interrupt morphing and configuration, circuits, systems and processes.
  15. Ellison,Carl M.; Golliver,Roger A.; Herbert,Howard C.; Lin,Derrick C.; McKeen,Francis X.; Neiger,Gilbert; Reneris,Ken; Sutton,James A.; Thakkar,Shreekant S.; Mittal,Millind, Managing a secure environment using a chipset in isolated execution mode.
  16. Sundby, James Toner, Means to detect a missing pulse and reduce the associated PLL phase bump.
  17. McKeen,Francis X.; Reneris,Ken; Grawrock,David W., Mechanism to secure computer output from software attack using isolated execution.
  18. Schwarz Roland H. (Geneva CHX), Memory system having two-level security system for enhanced protection against unauthorized access.
  19. Brownlee Paul M. (Gilbert AZ) Bills Jeffery E. (Chandler AZ), Method and apparatus for enhanced security of a data processor.
  20. Helbig ; Sr. Walter A, Method and apparatus for enhancing computer system security.
  21. Kocher Paul C. ; Jaffe Joshua M. ; Jun Benjamin C., Method and apparatus for preventing piracy of digital content.
  22. Mittal,Millind, Method and apparatus for secure execution using a secure memory partition.
  23. Bulusu,Mallik; Zimmer,Vincent J., Method and apparatus for trusted blade device computing.
  24. Brannock, Kirk D.; Cheng, Antonio S., Method and apparatus for verifying authenticity of initial boot code.
  25. Wolfe Robert L. ; Pinals Jeffrey, Method and system for using a communication network to supply targeted streaming advertising in interactive media.
  26. Angelo, Michael F.; Michels, Peter J., Method for securely creating, storing and using encryption keys in a computer system.
  27. Christie,David S.; Strongin,Geoffrey S.; McGrath,Kevin J., Method for selectively disabling interrupts on a secure execution mode-capable processor.
  28. McDevitt,Hugh W.; Spanel,Carol; Walls,Andrew D., Method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency.
  29. Little Wendell L. ; Curry Stephen M. ; Grider Steven N. ; Thrower Mark L. ; Hass Steven N. ; Bolan Michael L. ; Fieseler Ricky D. ; Harrington Bradley M., Microcircuit with memory that is protected by both hardware and software.
  30. Sawase Terumi (Sayama JPX) Nakamura Hideo (Himodemachi JPX) Hagiwara Yoshimune (Hachioji JPX) Kihara Toshimasa (Tachikawa JPX) Matsubara Kiyoshi (Kodaira JPX) Yamaura Tadashi (Kokubunji JPX), Microcomputer having a PROM including data security and test circuitry.
  31. Nakamura Hideo (Tokyo JPX) Sawase Terumi (Sayama JPX), Microcomputer incorporating a nonvolatile semiconductor memory.
  32. Eyer Mark K. (San Diego CA) Moroney Paul (Cardiff-By-The-Sea CA), Microcomputer with internal ram security during external program mode.
  33. Kase Kiyoshi (Chiba JPX) Suzuki Minoru (Tokyo JPX), Microprocessor having a protection circuit to insure proper instruction fetching.
  34. Michael C. Fischer ; Josh Hogan ; Terril Hurst ; Daniel Y. Abramovitch ; Carl Taussig, Missing pulse detector using synchronous detection.
  35. Ducharme,Paul, Monolithic semiconductor device for preventing external access to an encryption key.
  36. Davis Derek L., Optimized security functionality in an electronic system.
  37. Okada, Takayuki, Processor with a function to prevent illegal execution of a program, an instruction executed by a processor and a method of preventing illegal execution of a program.
  38. Force Gordon (San Jose CA) Davis Timothy D. (Arlington TX) Duncan Richard L. (Bedford TX) Norcross Thomas M. (Arlington TX) Shay Michael J. (Arlington TX) Short Timothy A. (Duncanville TX), Programmable distributed personal security.
  39. Hartmann Robert F. (San Jose CA) Chan Yiu-Fai (Saratoga CA) Frankovich Robert J. (Cupertino CA) Ou Jung-Hsing (Sunnyvale CA) So Hock C. (Milpitas CA) Wong Sau-Ching (Hillsborough CA), Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits.
  40. Kablotsky,Joshua, Programmable processor supporting secure mode.
  41. Pombo Raul (Plantation FL) Borras Jaime (Hialeah FL) Bron Michel (Lausanne CHX), Protection circuit for a microprocessor.
  42. Victor, Alan, Quality of phase lock and loss of lock detector.
  43. Lee Robert D. (Denton TX) Kurkowski Hal (Dallas TX) Bolan Michael L. (Dallas TX), Registered outputs for a memory device.
  44. May, Marcus W., SOC with low power and performance modes.
  45. England,Paul; Peinado,Marcus, Saving and retrieving data based on symmetric key encryption.
  46. Laczko, Sr., Frank L.; Ferguson, Edward, Secure computing device having boot read only memory verification of program code.
  47. Holtey Thomas O. (Newton MA) Wilson Peter J. (Leander TX), Secure memory card.
  48. Paatero,Lauri, Secure mode controlled memory.
  49. Dahan,Franck; Roussel,Christian; Chateau,Alain; Cumming,Peter, Secure mode for processors supporting MMU.
  50. Dahan,Franck; Roussel,Christian; Chateau,Alain; Cumming,Peter, Secure mode for processors supporting interrupts.
  51. Sibert,W. Olin, Secure processing unit systems and methods.
  52. Goto, Seiji, Secure processor.
  53. Mihm, Jr., Thomas J.; Uner, Eric R., Secure storage of data.
  54. Guttag Karl M. (Houston TX) Nussrallah Steve (Richardson TX), Security bit for designating the security status of information stored in a nonvolatile memory.
  55. Padgaonkar Ajay J. (9617 S. 43rd Pl. Phoenix AZ 85044) Mitra Sumit K. (8860 S. Drea La. Tempe AZ 85284), Security for digital signal processor program memory.
  56. Fujiwara,Makoto; Nemoto,Yusuke; Yasui,Junichi; Maeda,Takuji; Ito,Takayuki; Yamada,Yasushi; Inoue,Shinji, Semiconductor device including encryption section, semiconductor device including external interface, and content reproduction method.
  57. Wakimoto Yasuhiro (Yokohama JPX) Suzuki Tetsuo (Tokyo JPX), Single chip microcomputer having unauthorized memory space access protection.
  58. Horning,James J.; Sibert,W. Olin; Tarjan,Robert E.; Maheshwari,Umesh; Horne,William G.; Wright,Andrew K.; Matheson,Lesley R.; Owicki,Susan K., Software self-defense systems and methods.
  59. Hu, Guoan, Symmetric key based secure microprocessor and its applications.
  60. Lee,Ming Lung, System and method for bios setup.
  61. Burghardt Martin (Oberneuching NY DEX) Berman Eric (Hicksville NY) Padgaonkar Ajay (Sugarland TX) Allen Ray (Mesa AZ), System and method for protecting contents of microcontroller memory by providing scrambled data in response to an unauth.
  62. Cooney Henry G. (Kettering OH), System and method for providing for secure encryptor key management.
  63. Sibigtroth James M. (Round Rock TX), System for securing a data processing system and method of operation.
  64. Morgan, Andrew; Anvin, H. Peter, System with secure cryptographic capabilities using a hardware specific digital secret.
  65. Ginter Karl L. ; Shear Victor H. ; Sibert W. Olin ; Spahn Francis J. ; Van Wie David M., Systems and methods for secure transaction management and electronic rights protection.
  66. Hashimoto,Mikio; Teramoto,Keiichi; Saito,Takeshi; Shirakawa,Kenji; Fujimoto,Kensaku, Tamper resistant microprocessor.
  67. Watt, Simon Charles; Dornan, Christopher Bentley; Orion, Luc; Chaussade, Nicolas; Belnet, Lionel; Brochier, Stephane Eric Sebastian; Mansell, David Hennah; Symes, Dominic Hugo, Task following between multiple operating systems.
  68. Watt,Simon Charles; Dornan,Christopher Bentley; Orion,Luc; Chaussade,Nicolas; Belnet,Lionel; Brochier,Stephane Eric Sebastien; Mansell,David Hennah; Callan,Jonathan Sean, Vectored interrupt control within a system having a secure domain and a non-secure domain.
  69. Doi Bryan C. (Fremont CA) Thomas Steven D. (Palm Dale CA) Coli Vincent J. (San Jose CA) Giglio Vito D. (Canoga Park CA), Verifiable security circuitry for preventing unauthorized access to programmed read only memory.
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