A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalli
A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact is aligned to the first transistors with less than about 40 nm alignment error, a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.
대표청구항▼
1. A semiconductor device, comprising: a first layer comprising monocrystalline material and first transistors, said first transistors overlaid by a first isolation layer;a second layer comprising second transistors and overlaying said first isolation layer, said second transistors comprising a mono
1. A semiconductor device, comprising: a first layer comprising monocrystalline material and first transistors, said first transistors overlaid by a first isolation layer;a second layer comprising second transistors and overlaying said first isolation layer, said second transistors comprising a monocrystalline material;at least one contact to said second transistors, wherein said at least one contact is aligned to said first transistors with less than about 40 nm alignment error,a first set of external connections underlying said first layer to connect said device to external devices;a second set of external connections overlying said second layer to connect said device to external devices; andan interconnection layer in-between said first layer and said second layer, wherein said interconnection layer comprises copper or aluminum. 2. The semiconductor device according to claim 1, wherein said second transistors comprise P type transistors and N type transistors. 3. The semiconductor device according to claim 1, further comprising: a back-bias structure for at least one of said second transistors. 4. The semiconductor device according to claim 1, wherein said second layer comprises a node for wireless connection to external devices. 5. The semiconductor device according to claim 1, wherein said first set of external connections comprise through-silicon-vias (“TSV”). 6. The semiconductor device according to claim 1, wherein said second set of external connections comprise micro-bumps. 7. The semiconductor device according to claim 1, wherein said second transistors are horizontally oriented transistors. 8. A semiconductor device, comprising: a first layer comprising monocrystalline material and first transistors, said first transistors overlaid by a first isolation layer;a second layer comprising second transistors and overlaying said first isolation layer, said second transistors comprising a monocrystalline material;at least one contact to said second transistors, wherein said at least one contact is aligned to said first transistors with less than about 40 nm alignment error,a first set of external connections underlying said first layer to connect said device to external devices; anda second set of external connections overlying said second layer to connect said device to external devices, wherein said second layer comprises a node for wireless connection to external devices. 9. The semiconductor device according to claim 8, wherein said second transistors comprise P type transistors and N type transistors. 10. The semiconductor device according to claim 8, further comprising: a back-bias structure for at least one of said second transistors. 11. The semiconductor device according to claim 8, further comprising: an interconnection layer in-between said first layer and said second layer, wherein said interconnection layer comprises copper or aluminum. 12. The semiconductor device according to claim 8, wherein said first set of external connections comprise through-silicon-vias (“TSV”). 13. The semiconductor device according to claim 8, wherein said second set of external connections comprise micro-bumps. 14. The semiconductor device according to claim 8, wherein said second transistors are horizontally oriented transistors. 15. A semiconductor device, comprising: a first layer comprising monocrystalline material and first transistors, said first transistors overlaid by a first isolation layer;a second layer comprising second transistors and overlaying said first isolation layer, said second transistors comprising a monocrystalline material;at least one contact to said second transistors, wherein said at least one contact is aligned to said first transistors with less than about 40 nm alignment error,a first set of external connections underlying said first layer to connect said device to external devices; anda second set of external connections overlying said second layer to connect said device to external devices. 16. The semiconductor device according to claim 15, wherein said second transistors comprise P type transistors and N type transistors. 17. The semiconductor device according to claim 15, further comprising: a back-bias structure for at least one of said second transistors. 18. The semiconductor device according to claim 15, further comprising: an interconnection layer in-between said first layer and said second layer, wherein said interconnection layer comprises copper or aluminum. 19. The semiconductor device according to claim 15, wherein said first set of external connections comprise through-silicon-vias (“TSV”). 20. The semiconductor device according to claim 15, wherein said second transistors are horizontally oriented transistors.
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Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including corner short configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including merged-via configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and chamfer short test areas.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells.
Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure.
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