System and method for reducing reconfiguration power
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-019/173
G06F-017/50
H03K-019/177
출원번호
US-0638934
(2010-10-21)
등록번호
US-8912820
(2014-12-16)
국제출원번호
PCT/US2010/053487
(2010-10-21)
§371/§102 date
20121001
(20121001)
국제공개번호
WO2011/123151
(2011-10-06)
발명자
/ 주소
Huang, Randy R.
Voogel, Martin
Hu, Jingcao
Teig, Steven
출원인 / 주소
Tabula, Inc.
대리인 / 주소
Adeli LLP
인용정보
피인용 횟수 :
3인용 특허 :
141
초록▼
A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits
A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.
대표청구항▼
1. An integrated circuit (“IC”) comprising: a group of reconfigurable circuits, each of the reconfigurable circuits for configurably performing a plurality of different operations in different reconfiguration cycles based on stored configuration data;a select driver for selecting different sets of s
1. An integrated circuit (“IC”) comprising: a group of reconfigurable circuits, each of the reconfigurable circuits for configurably performing a plurality of different operations in different reconfiguration cycles based on stored configuration data;a select driver for selecting different sets of stored configuration data in different reconfiguration cycles for the group of reconfigurable circuits, wherein the select driver comprises a clock input for receiving clock signals, wherein the select driver selects a different set of stored configuration data in each reconfiguration cycle in which the select driver receives a clock signal; anda gating circuit for selectively blocking a set of clock signals from reaching the clock input in a set of reconfiguration cycles controlled by configuration data of the gating circuit. 2. The IC of claim 1 further comprising a plurality of multiplexers (MUXs) for selectively providing the different sets of configuration data to the reconfigurable circuits. 3. The IC of claim 2, wherein at least one of the plurality of MUXs comprises a set of inputs that determine which of a plurality of stored configuration data values will be provided to the reconfigurable circuit. 4. The IC of claim 3, wherein the set of inputs are communicatively coupled to the select driver. 5. The IC of claim 2, wherein the MUXs are one-hot select MUXs. 6. The IC of claim 2, wherein the select driver selects different sets of stored configuration data by activating a selected set of inputs of the MUXs, wherein the inputs are communicatively coupled to a set of stored configuration data, wherein activating the selected set of inputs comprises communicatively coupling the set of inputs to a set of outputs of the MUXs. 7. The IC of claim 1, wherein the gating circuit comprises a set of configuration storage elements for storing configuration values that determine whether to block the clock signal, wherein each of the configuration values determines whether to block the clock signal in a particular reconfiguration cycle. 8. The IC of claim 1, wherein the select driver cyclically selects different sets of stored configuration data from among a sequence of sets of stored configuration data when receiving a plurality of clock signals, wherein selecting a different set of stored configuration data comprises switching from one stored configuration data set in the sequence to another stored configuration data set in the sequence. 9. The IC of claim 1, wherein the gating circuit comprises a set of logic circuits for imposing additional conditions on the blocking of the clock signal. 10. The IC of claim 9, wherein the additional conditions comprise a configuration value that determines whether to prevent the blocking in all reconfiguration cycles. 11. The IC of claim 1, wherein blocking the clock signal comprises preventing the clock signal from reaching the select driver, wherein preventing the clock signal from reaching the select driver prevents the select driver from selecting a different set of stored configuration data. 12. An integrated circuit (“IC”) comprising: (i) a plurality of reconfigurable circuits, each of the reconfigurable circuits for configurably performing a plurality of different operations in different reconfiguration cycles; (ii) a plurality of select drivers, each select driver for reconfiguring a group of the reconfigurable circuits; and (iii) a plurality of gating circuits, each gating circuit associated with at least one of the select drivers, the gating circuit for selectively blocking the associated at least one select driver from reconfiguring the group of the reconfigurable circuits. 13. The IC of claim 12, wherein each of the select drivers comprises a set of select lines that determine which of a plurality of stored configurations are active in each of a plurality of reconfiguration cycles, wherein when the gating circuit blocks the associated select driver from reconfiguring the group, the select driver maintaining value on the set of select lines for at least two consecutive reconfiguration cycles. 14. The IC of claim 12 further comprising a plurality of reconfiguration cycle counters that each cyclically provides different signals that (i) determine which configuration of a gating circuit is active in each of a plurality of different reconfiguration cycles and (ii) determine which configuration the select driver selects in each of a plurality of reconfiguration cycles in which the select driver is not blocked from reconfiguring the group of reconfigurable circuits. 15. An electronic device comprising: a memory device for storing configuration data; andan integrated circuit (“IC”) comprising: a group of reconfigurable circuits, each of the reconfigurable circuits for configurably performing a plurality of different operations in different reconfiguration cycles based on the stored configuration data;a select driver for selecting different sets of stored configuration data in different reconfiguration cycles for the group of reconfigurable circuits, wherein the select driver comprises a clock input for receiving clock signals, wherein the select driver selects a different set of stored configuration data in each reconfiguration cycle in which the select driver receives a clock signal; anda gating circuit for selectively blocking a set of clock signals from reaching the clock input in a set of reconfiguration cycles controlled by configuration data of the gating circuit. 16. The electronic device of claim 15 further comprising a plurality of multiplexers (MUXs) for selectively providing different sets of configuration data to the reconfigurable circuits, wherein at least one of the plurality of MUXs comprises a set of inputs that determine which of a plurality of stored configuration data values will be provided to the reconfigurable circuit, wherein the set of inputs are communicatively coupled to the select driver. 17. The electronic device of claim 16, wherein the MUXs are one-hot select MUXs. 18. The electronic device of claim 16, wherein the select driver selects different sets of stored configuration data by activating a selected set of inputs of the MUXs, wherein the inputs are communicatively coupled to a set of stored configuration data, wherein activating the selected set of inputs comprise communicatively coupling the set of inputs to a set of outputs of the MUXs. 19. The electronic device of claim 15, wherein the gating circuit comprises a set of configuration storage elements for storing configuration values that determine whether to block the clock signal, wherein each of the configuration values determine whether to block the clock signal in a particular reconfiguration cycle. 20. The electronic device of claim 15, wherein the select driver cyclically selects different sets of stored configuration data from among a sequence of sets of stored configuration data when receiving a plurality of clock signals, wherein selecting a different set of stored configuration data comprises switching from one stored configuration data set in the sequence to another stored configuration data set in the sequence. 21. The electronic device of claim 15, wherein the gating circuit comprises a set of logic circuits for imposing additional conditions on the blocking of the clock signal, wherein the additional conditions comprise a configuration value that determines whether to prevent the blocking in all reconfiguration cycles. 22. The electronic device of claim 15, wherein blocking the clock signal comprises preventing the clock signal from reaching the select driver, wherein preventing the clock signal from reaching the select driver prevents the select driver from selecting a different set of stored configuration data. 23. An electronic device comprising: a memory device for storing configuration data; andan integrated circuit (“IC”) comprising: a plurality of reconfigurable circuits, each of the reconfigurable circuits for configurably performing a plurality of different operations in different reconfiguration cycles based on the stored configuration data;a plurality of select drivers, each select driver for reconfiguring a group of the reconfigurable circuits; anda plurality of gating circuits, each gating circuit associated with at least one of the select drivers, the gating circuit for selectively blocking the associated at least one select driver from reconfiguring the group of the reconfigurable circuits. 24. The electronic device of claim 23, wherein each of the select drivers comprises a set of select lines that determine which of a plurality of stored configurations are active in each of a plurality of reconfiguration cycles, wherein when the gating circuit blocks the associated select driver from reconfiguring the group, the select driver maintaining a value on the set of select lines for at least two consecutive reconfiguration cycles. 25. The electronic device of claim 23 further comprising a plurality of reconfiguration cycle counters that each cyclically provides different signals that (i) determine which configuration of a gating circuit is active in each of a plurality of different reconfiguration cycles and (ii) determine which configuration the select driver selects in each of a plurality of reconfiguration cycles in which the select driver is not blocked from reconfiguring the group of reconfigurable circuits.
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이 특허에 인용된 특허 (141)
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Inoue Kazunari (Hyogo JPX) Fudeyasu Yoshio (Hyogo JPX), Dual port memory effecting transfer of data between a serial register and an arbitrary memory block.
Nguyen Bai ; Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Wong Jack T. ; Chang Herman M., Efficient interconnect network for use in FPGA device having variable grain architecture.
Kant,Shree; Tam,Kenway; Kongetira,Poonacha P.; Lin,Yuan Jung D; Liu,Zhen W.; Aingaran,Kathirgamar, Efficient method of data transfer between register files and memories.
Agrawal, Om P.; Fontana, Fabiano; Bosco, Gilles M., Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use.
Iadanza Joseph Andrew ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Field programmable memory array.
Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
Poplingher Mircea ; Chen Wenliang ; Suryanarayanan Ganesh ; Chen Wayne W. ; Lo Roger Y., Memory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycle.
Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC.
Jacobson, Neil G.; Flores Jr., Emigdio M.; Srivastava, Sanjay; Dai, Bin; Mao, Sungnien Jerry, Method for concurrently programming a plurality of in-system-programmable logic devices by grouping devices to achieve minimum configuration time.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Method of operating a field programmable memory array with a field programmable gate array.
Dai Wei-Jin (Cupertino CA) Galbiati ; III Louis (Mountain View CA) Varghese Joseph (Sunnyvale CA) Bui Dam V. (Milpitas CA) Sample Stephen P. (Mountain View CA), Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Method of time multiplexing a programmable logic device.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Programmable address decoder for field programmable memory array.
Motomura Masato,JPX, Programmable logic IC having memories for previously storing a plurality of configuration data and a method of reconfigurating same.
New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
Blodget, Brandon J.; McMillan, Scott P.; James-Roxby, Philip B.; Sundararajan, Prasanna; Keller, Eric R.; Curd, Derek R.; Kalra, Punit S.; LeBlanc, Richard J.; Eck, Vincent P., Reconfiguration of a programmable logic device using internal control.
Balasubramanian,Rabindranath; Zhu,Limin; Speers,Theodore; Bakker,Gregory, System-on-a-chip integrated circuit including dual-function analog and digital inputs.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.
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