최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0570943 (2009-09-30) |
등록번호 | US-8914590 (2014-12-16) |
우선권정보 | DE-102 36 269 (2002-08-07); DE-102 36 271 (2002-08-07); DE-102 36 272 (2002-08-07); WO-PCT/EP02/10065 (2002-08-16); DE-102 38 172 (2002-08-21); DE-102 38 173 (2002-08-21); DE-102 38 174 (2002-08-21); DE-102 40 000 (2002-08-27); DE-102 40 022 (2002-08-27); WO-PCT/DE02/03278 (2002-09-03); DE-102 41 812 (2002-09-06); WO-PCT/EP02/10084 (2002-09-09); DE-102 43 322 (2002-09-18); WO-PCT/EP02/10464 (2002-09-18); WO-PCT/EP02/10479 (2002-09-18); WO-PCT/EP02/10536 (2002-09-19); WO-PCT/EP02/10572 (2002-09-19); EP-02022692 (2002-10-10); EP-02027277 (2002-12-06); DE-103 00 380 (2003-01-07); WO-PCT/DE03/00152 (2003-01-20); WO-PCT/DE03/00624 (2003-01-20); WO-PCT/DE03/00489 (2003-02-18); DE-103 10 195 (2003-03-06); WO-PCT/DE03/00942 (2003-03-21); DE-103 15 295 (2003-04-04); EP-03009906 (2003-04-30); DE-103 21 834 (2003-05-15); EP-03013694 (2003-06-17); EP-03015015 (2003-07-02) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 2 인용 특허 : 566 |
In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurabl
In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.
1. A processor chip comprising: a plurality of processor cores, including at least one processor having a plurality of ALUs;a plurality of local memories comprising copies of main memory areas;a cache controller controlling at least one of the local memories; wherein:the processor chip has multi-thr
1. A processor chip comprising: a plurality of processor cores, including at least one processor having a plurality of ALUs;a plurality of local memories comprising copies of main memory areas;a cache controller controlling at least one of the local memories; wherein:the processor chip has multi-thread capabilities; andthe cache controller is adapted to receive prefetch requests during execution of a first thread and to prefetch data during the execution of a second thread;wherein the prefetch commands are software instructions generated by a compiler, andat least some of the prefetch requests are burst requests to the cache controller; and the burst request comprising a vector stride request. 2. The processor chip of claim 1 wherein a vector stride comprises a displacement of data between two memory elements. 3. The processor chip of claim 2 wherein the displacement of data between two memory elements is greater than the size of a cache line. 4. A method for operating a processor chip that comprises a plurality of processor cores including at least one processor having a plurality of ALUs and having multi-thread capabilities, and that further comprises a plurality of local memories comprising copies of main memory areas, at least some of the local memories operating as first level cache, the method comprising: prefetching data from the main memory areas into the local memories; the prefetching being initiated by a prefetch command during execution of a first thread; andprefetching data during the execution of a second thread;the prefetch command is a software instruction generated by a compiler;wherein the prefetching step comprises prefetching a vector stride. 5. The method according to claim 4, wherein at least some parts of the first level cache are shared between the processor cores. 6. The method of claim 4 wherein a vector stride comprises a displacement of data between two memory elements. 7. The method of claim 6 wherein the displacement of data between two memory elements is greater than the size of a cache line.
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