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Embedded wafer level package for 3D and package-on-package applications, and method of manufacture

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/31
  • H01L-023/538
  • H01L-023/00
  • H01L-023/498
  • H01L-025/00
  • H01L-021/48
  • H01L-025/10
  • H05K-001/18
출원번호 US-0312562 (2011-12-06)
등록번호 US-8916481 (2014-12-23)
발명자 / 주소
  • Gan, Kah Wee
  • Huang, Yaohuang
  • Jin, Yonggang
출원인 / 주소
  • STMicroelectronics Pte Ltd.
대리인 / 주소
    Seed IP Law Group PLLC
인용정보 피인용 횟수 : 13  인용 특허 : 54

초록

A process for manufacturing a 3D or PoP semiconductor package includes forming a redistribution layer on a reconstituted wafer, then laser drilling a plurality of apertures in the reconstituted wafer, extending from an outer surface of the reconstituted wafer to intersect electrical traces in the fi

대표청구항

1. A method, comprising: forming a reconstituted wafer by embedding a first semiconductor die in a first molding compound layer, with a face of the first semiconductor die lying substantially in a first plane with a face of the first molding compound layer of the reconstituted wafer;positioning a fi

이 특허에 인용된 특허 (54)

  1. Yamano, Takaharu; Iizuka, Hajime; Sakaguchi, Hideaki; Kobayashi, Toshio; Arai, Tadashi; Kobayashi, Tsuyoshi; Koyama, Tetsuya; Iida, Kiyoaki; Mashima, Tomoaki; Tanaka, Koichi; Kunimoto, Yuji; Yanagisawa, Takashi, Chip embedded substrate and method of producing the same.
  2. Lee, Chang-Chi; Chen, Shih-Kuang; Chang, Yuan-Ting, Chip package structure and method of manufacturing the same.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages.
  4. Kinsman, Larry D.; Akram, Salman, Chip scale packages performed by wafer level processing.
  5. Shen, Chi-Chih; Chen, Jen-Chuan; Wang, Wei-Chung, Circuit substrate and method of fabricating the same and chip package structure.
  6. Ma Qing ; Mu Chun ; Fujimoto Harry, Direct build-up layer on an encapsulated die package.
  7. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  8. Khan, Rezaur Rahman; Zhao, Sam Ziqun, Interconnect structure and formation for package stacking of molded plastic area array package.
  9. Child, Craig, Interconnect structure for a semiconductor device.
  10. Tsukada Yutaka (Shiga JPX), Interconnect structure with replaced semiconductor chips.
  11. Fukase,Katsuya; Wakabayashi,Shinichi, Interposer method of fabricating same, and semiconductor device using the same having two portions with different constructions.
  12. Kishore K. Chakravorty, Low cost chip size package and method of fabricating the same.
  13. Tsukada Yutaka (Shiga JPX), Method for replacing semiconductor chips.
  14. Corisis, David J.; Chong, Chin Hui; Lee, Choon Kuan, Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices.
  15. Pu, Han-Ping; Huang, Chih-Ming; Huang, Chien-Ping, Module device of stacked semiconductor packages and method for fabricating the same.
  16. Inoue, Akinobu, Multiple electronic component containing substrate.
  17. King Michael O. (Fremont CA) Keshner Marvin S. (Mtn. View CA), Package for water-scale semiconductor devices.
  18. Kang, Teck-Gyu, Package on package configurations with embedded solder balls and interposal layer.
  19. Wasielewski J. Paul (Scottsdale AZ), Packaging module for a semiconductor wafer.
  20. Ohshima Osamu,JPX ; Udagawa Yoshiaki,JPX ; Suzuki Masahiro,JPX ; Nishiyama Takeshi,JPX, Printed wiring board with mounted circuit element using a terminal density conversion board.
  21. Kajiki, Atsunori, Semiconductor apparatus and manufacturing method thereof.
  22. Chen, Kun-Ching; Ding, Yi-Chuan; Ou, In-De, Semiconductor build-up package.
  23. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  24. Jobetto,Hiroyasu; Mihara,Ichiro, Semiconductor device.
  25. Mori, Kentaro; Kikuchi, Katsumi; Yamamichi, Shintaro, Semiconductor device and fabrication method.
  26. Yamane,Tae; Katsuno,Jyouji; Fukaya,Kiyohisa, Semiconductor device and fabrication method of the same.
  27. Yamaguchi,Tadashi, Semiconductor device and manufacturing method thereof.
  28. Pagaila, Reza A.; Lin, Yaojian; Koo, Jun Mo, Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation.
  29. Lin, Yaojian; Bao, Xusheng; Chen, Kang; Fang, Jianmin, Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP.
  30. Camacho, Zigmund R.; Merilo, Dioscoro A.; Pisigan, Jairus L.; Dahilig, Frederick R., Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers.
  31. Jobetto, Hiroyasu, Semiconductor device and method of manufacturing the same.
  32. Jobetto,Hiroyasu, Semiconductor device and method of manufacturing the same.
  33. Aoyagi,Akiyoshi, Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument.
  34. Oh, JiHoon; Lee, SinJae; Kim, JinGwan, Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die.
  35. Wakabayashi,Takeshi; Mihara,Ichiro, Semiconductor device comprising a plurality of semiconductor constructs.
  36. Yoshihiro Tomita JP, Semiconductor device comprising a semiconductor element mounted on a substrate and covered by a wiring board.
  37. Okada, Osamu; Jobetto, Hiroyasu, Semiconductor device having adhesion increasing film to prevent peeling.
  38. Yamada,Shigeru, Semiconductor device having packaging structure.
  39. Negishi, Yuji, Semiconductor device having semiconductor structure bodies on upper and lower surfaces thereof, and method of manufacturing the same.
  40. Jobetto,Hiroyasu, Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same.
  41. Kobayashi, Kazutaka; Arai, Tadashi; Kurihara, Takashi, Semiconductor element, semiconductor element mounted board, and method of manufacturing semiconductor element.
  42. Mistry, Addi B.; Haas, Joseph M.; Kiffe, Dennis O.; Kleffner, James H.; Wilde, Daryl R., Semiconductor package with multiple sides having package contacts.
  43. Senba Naoji,JPX ; Shimada Yuzo,JPX ; Utsumi Kazuaki,JPX ; Tokuno Kenichi,JPX ; Morizaki Ikushi,JPX ; Dohya Akihiro,JPX ; Bonkohara Manabu,JPX, Semiconductor packing stack module and method of producing the same.
  44. Fjelstad Joseph, Solder ball placement fixtures and methods.
  45. Mallik,Debendra; Ichikawa,Kinya; Sterrett,Terry L.; Swan,Johanna, Stackable integrated circuit packaging.
  46. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.
  47. Song, Sungmin; Myung, Junwoo; Jang, Byoung Wook, Stacked integrated circuit package system with intra-stack encapsulation.
  48. Longo, Joseph Marco; Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  49. Avni, Noam; Zeevi, Amit; Navot, Yavir; Haller, Motti, System, method and apparatus employing crystal oscillator.
  50. Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.
  51. Lin,Charles W. C.; Chiang,Cheng Lien, Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture.
  52. Jin, Yong Gang; Shin, Won Sun, Torch bump.
  53. Takayama, Jun, Transparent member in a solid-state image pick-up apparatus supported through use of micro-lenses larger in size than pixel micro-lenses and a method for producing the micro-lenses and transparent member.
  54. Tazunoki Masanori (Nishitama JPX) Mishimagi Hiromitsu (Akishima JPX) Homma Makoto (Hamura JPX) Sakuta Toshiyuki (Hamura JPX) Nakamura Hisashi (Ohme JPX) Sasaki Keiji (Musashino JPX) Enomoto Minoru (T, Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein.

이 특허를 인용한 특허 (13)

  1. Wang, Zhiqi; Li, Junjie; Yang, Ying; Yu, Qiong; Wang, Wei, Chip to wafer package with top electrodes and method of forming.
  2. Razdan, Sandeep; Patel, Vipulkumar; Traverso, Matthew J., Fan-out wafer level integration for photonic chips.
  3. Pan, Kuo Lung; Liu, Chung-Shi; Tsai, Hao-Yi; Chen, Yu-Feng; Cheng, Yu-Jen, Integrated circuit package and method of forming same.
  4. Pan, Kuo Lung; Liu, Chung-Shi; Tsai, Hao-Yi; Chen, Yu-Feng; Cheng, Yu-Jen, Integrated circuit package and method of forming same.
  5. Heikkinen, Mikko; Sääski, Jarmo, Method for manufacturing an electronic assembly.
  6. Lu, Chung-Yu; Hu, Hsien-Pin; Yen, Hsiao-Tsung; Liu, Tzuan-Horng; Huang, Shih-Wen; Hou, Shang-Yun; Jeng, Shin-Puu, Methods and apparatus of packaging with interposers.
  7. Lu, Chung-Yu; Hu, Hsien-Pin; Yen, Hsiao-Tsung; Liu, Tzuan-Horng; Huang, Shih-Wen; Hou, Shang-Yun; Jeng, Shin-Puu, Methods and apparatus of packaging with interposers.
  8. Lin, Charles W. C.; Wang, Chia-Chung, Package-on-package semiconductor assembly having bottom device confined by dielectric recess.
  9. Fillion, Raymond Albert; Nagarkar, Kaustubh Ravindra, Semiconductor logic device and system and method of embedded packaging of same.
  10. Miyakoshi, Takeshi; Hosoyamada, Sumikazu; Kumagaya, Yoshikazu; Chikai, Tomoshige; Nakamura, Shingo; Matsubara, Hiroaki; Sakumoto, Shotaro, Semiconductor package.
  11. Miyakoshi, Takeshi; Hosoyamada, Sumikazu; Kumagaya, Yoshikazu; Chikai, Tomoshige; Nakamura, Shingo; Matsubara, Hiroaki; Sakumoto, Shotaro, Semiconductor package.
  12. Wang, Lung-Yuan; Chiang, Cheng-Chia; Hsu, Chu-Chi; Shih, Chia-Kai; Huang, Shu-Huei, Semiconductor package and fabrication method thereof.
  13. Ryu, Seung-Kwan; Kwon, Yonghwan; Choi, Yun Seok; Jo, Chajea; Cho, Taeje, Semiconductor package and method of fabricating the same.
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