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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0959455 (2013-08-05) |
| 등록번호 | US-8921914 (2014-12-30) |
| 발명자 / 주소 |
|
| 출원인 / 주소 |
|
| 대리인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 0 인용 특허 : 1473 |
Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected
Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.
1. An electronic device comprising: a substrate having a pair of diffused regions with a diffusion type opposite that of the substrate;a plurality of dielectric layers disposed over the substrate, the plurality of dielectric layers comprising ion nucleation sites embedded in a surface of the plurali
1. An electronic device comprising: a substrate having a pair of diffused regions with a diffusion type opposite that of the substrate;a plurality of dielectric layers disposed over the substrate, the plurality of dielectric layers comprising ion nucleation sites embedded in a surface of the plurality of dielectric layers;a plurality of layers of electrically isolated nanocrystals disposed upon the plurality of dielectric layers, each electrically isolated nanocrystal disposed from a respective ion implanted material of the ion nucleation sites, the ion implanted material being of a material different from the electrically isolated nanocrystals, each layer of the plurality of layers of electrically isolated nanocrystals vertically spaced from the other layers of electrically isolated nanocrystals; anda control gate disposed above the plurality of dielectric layers. 2. The electronic device of claim 1 wherein at least one of the plurality of dielectric layers does not comprise any nanocrystals. 3. The electronic device of claim 2 wherein the at least one of the plurality of dielectric layers without the nanocrystals is disposed between the substrate and the plurality of dielectric layers with the electrically isolated nanocrystals. 4. The electronic device of claim 3 wherein the at least one of the plurality of dielectric layers without the nanocrystals comprises one of silicon oxide, silicon nitride, silicon oxynitride, alumina, titanium dioxide, hafnium dioxide, tantalum dioxide, or barium titanate. 5. The electronic device of claim 1 wherein the electrically isolated nanocrystals comprise one of metal nanocrystals, insulating nanocrystals, or combinations of metal nanocrystals and insulating nanocrystals. 6. The electronic device of claim 1 wherein the substrate comprises one of amorphous silicon, polycrystalline silicon, germanium, or a compound semiconductor. 7. The electronic device of claim 1 wherein the plurality of electrically isolated nanocrystals are disposed over the substrate between the pair of diffused regions. 8. The electronic device of claim 1 wherein adjacent layers of the plurality of layers of electrically isolated nanocrystals are separated by a dielectric layer. 9. The electronic device of claim 1 wherein the electronic device is a non-volatile memory device. 10. The method of claim 1 wherein the nanocrystals comprise platinum (Pt), rhodium (Rh), ruthenium (Ru), palladium (Pd), cobalt (Co), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), titanium oxide (TiOX), cobalt oxide (CoOX), ruthenium oxide (RuOX), hafnium oxide (HfOX), aluminum oxide (Al2O3), tungsten oxide (WOX), titanium carbide (TiC), tantalum carbide (TaC), or tungsten carbide (WC). 11. The method of claim 1 wherein the nanocrystals comprise combinations of two or more of platinum (Pt), rhodium (Rh), ruthenium (Ru), palladium (Pd), cobalt (Co), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), tungsten (W), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), titanium oxide (TiOX), cobalt oxide (CoOX), ruthenium oxide (RuOX), hafnium oxide (HfOX), aluminum oxide (Al2O3), tungsten oxide (WOX), titanium carbide (TiC), tantalum carbide (TaC), or tungsten carbide (WC). 12. A system comprising: a controller; andan electronic device coupled to the controller, the electronic device comprising a plurality of floating gate transistors, each floating gate transistor comprising: a source and a drain formed in a substrate and separated laterally from each other by a region;a plurality of gate dielectrics disposed above the substrate;a plurality of layers of isolated nucleation sites, each layer disposed in different gate dielectrics;a plurality of layers of electrically isolated nanocrystals, each layer disposed on a top surface of the different gate dielectrics with a substantially even statistical distribution above and across the region, each electrically isolated nanocrystal disposed from a respective ion implanted material of the ion nucleation sites, the ion implanted material being of a material different from the electrically isolated nanocrystals;an inter-gate dielectric disposed over the plurality of gate dielectrics; andforming a control gate electrode disposed over the inter-gate dielectric. 13. The system of claim 12 wherein the plurality of gate dielectrics comprise a first thickness and the inter-gate dielectric comprises a second thickness that is different than the first thickness. 14. The system of claim 12 wherein at least 80% of the electrically isolated nanocrystals have diameters within a range of approximately 0.5 nanometers to approximately 5 nanometers, and are separated from each other by a separation distance within a range from approximately 0.5 nanometers to approximately 5 nanometers. 15. The system of claim 12 wherein the nucleation sites in the gate dielectrics are substantially all on a top surface of the gate dielectrics. 16. The system of claim 12 wherein each electrically isolated nanocrystal is attached to its respective dielectric layer by its respective ion nucleation site formed by a defect including at least one of boron, nitrogen, neon, argon, krypton, platinum, ruthenium, rhodium, palladium, titanium, zirconium, hafnium, silicon, germanium, cobalt, or tantalum. 17. The system of claim 12 wherein the ion implanted material is located above the top ⅕ of each of the gate dielectric layers. 18. The system of claim 12 wherein the ion implanted material comprises inert gases or semiconductor materials. 19. The system of claim 18 wherein the inert gases comprise argon, neon, helium or xenon and the semiconductor materials comprise silicon, carbon, or germanium. 20. The system of claim 12 wherein each layer of electrically isolated nanocrystals comprises a floating gate. 21. A memory cell comprising: a channel region;a first dielectric material adjacent to the channel region;a plurality of nanoscale structures, each of the plurality of nanoscale structures seeded from ion implanted material of a respective nucleation site of a plurality of nucleation sites at least partially embedded in a surface of the first dielectric material opposite the channel region, the ion implanted material being of a material different from the plurality of nanoscale structures;a second dielectric material adjacent to the plurality of nanoscale structures; anda control gate adjacent to the second dielectric material. 22. The memory cell of claim 21, wherein the nanoscale structures comprise at least one of nanocrystals, nanowires and nanotubes. 23. The memory cell of claim 21, wherein the nanoscale structures comprises nanocrystals, and wherein the nanocrystals function as a floating gate of the memory cell. 24. The memory cell of claim 21, wherein the nanoscale structures comprise ruthenium nanocrystals. 25. The memory cell of claim 21, wherein the nucleation sites comprise atoms of the ion implanted material sticking out from the surface of the first dielectric material. 26. The memory cell of claim 21, wherein the nucleation sites comprise ions sticking out from the surface of the first dielectric material. 27. The memory cell of claim 21, wherein the channel region comprises polycrystalline silicon. 28. The memory cell of claim 21, wherein the channel region comprises silicon. 29. The memory cell of claim 21, wherein the channel region is between a source region and a drain region. 30. The memory cell of claim 21, wherein the plurality of nanoscale structures comprise a plurality of electrically isolated nanoscale structures. 31. The memory cell of claim 21, wherein the plurality of nanoscale structures are disposed upon the first dielectric material. 32. The memory cell of claim 21, wherein at least one of the plurality of nucleation sites at least partially embedded in a surface of the first dielectric material is only partially embedded into the surface of the first dielectric material. 33. The memory cell of claim 21, wherein at least one of the plurality of nucleation sites at least partially embedded in the surface of the first dielectric material is entirely embedded into the surface of the first dielectric material. 34. The memory cell of claim 21, wherein the ion implanted material of the plurality of nucleation sites is in the top 1 nanometer of the first dielectric material. 35. The memory cell of claim 21, wherein the ion implanted material of the plurality of nucleation sites is in the top ⅕th of the first dielectric material. 36. The memory cell of claim 21, wherein sizes of the plurality of nanoscale structures range from about 0.5 nanometers to about 5 nanometers. 37. The memory cell of claim 21, wherein average spacings between adjacent nanoscale structures of the plurality of nanoscale structures range from about 0.5 nanometers to about 5 nanometers. 38. The memory cell of claim 21, wherein a density of the plurality of nanoscale structures is greater than one nanoscale structure per 15 square nanometers. 39. A transistor comprising: a channel region;first dielectric material adjacent to the channel region;a plurality of nanoscale structures, each of the plurality of nanoscale structures seeded from ion implanted material of a respective nucleation site of a plurality of nucleation sites at least partially embedded in a surface of the first dielectric material opposite the channel region, the ion implanted material being of a material different from the plurality of nanoscale structures;second dielectric material adjacent to the plurality of nanoscale structures; anda control gate adjacent to the second dielectric. 40. A memory device comprising a plurality of memory cells, wherein each of the memory cells comprises: a channel region;first dielectric material adjacent to the channel region;a plurality of nanoscale structures, each of the plurality of nanoscale structures seeded from ion implanted material of a respective nucleation site of a plurality of nucleation sites at least partially embedded in a surface of the first dielectric material opposite the channel region, the ion implanted material being of a material different from the plurality of nanoscale structures;second dielectric material adjacent to the plurality of nanoscale structures; anda control gate adjacent to the second dielectric.
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