A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) with
A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.
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1. A method for forming a MOSFET, comprising: providing a substrate of a first conductivity type, having a substrate upper surface;forming a substrate cavity of a cavity depth in the substrate from the substrate upper surface, the substrate cavity having a cavity bottom and a cavity sidewall extendi
1. A method for forming a MOSFET, comprising: providing a substrate of a first conductivity type, having a substrate upper surface;forming a substrate cavity of a cavity depth in the substrate from the substrate upper surface, the substrate cavity having a cavity bottom and a cavity sidewall extending toward the substrate upper surface, the cavity sidewall having a lower sidewall portion and having an upper sidewall portion with a curved shape, via which the cavity sidewall joins the substrate upper surface;forming a dielectric liner on the cavity sidewall, wherein the dielectric liner has a lower liner portion of a lower liner thickness substantially on the lower sidewall portion, and wherein the dielectric liner has an upper liner portion proximate the upper sidewall portion and with an upper liner thickness, wherein the upper liner thickness exceeds the lower liner thickness in at least part of the upper sidewall portion;forming a gate conductor at least partly within the dielectric liner of the substrate cavity, the gate conductor having a first gate conductor portion proximate the lower liner portion, a second gate conductor portion overlying the first gate portion proximate the upper liner portion, and a third gate conductor portion above the substrate upper surface for a gate extension distance;forming one or more body regions in the substrate of a body region depth from the upper substrate surface, laterally proximate the dielectric liner and of a second opposite conductivity type; andforming one or more final source regions within the body regions, extending substantially to the substrate upper surface and proximate the dielectric liner, and having a lower source extremity of a source extremity depth beneath the substrate upper surface that is less than the body region depth, andwherein forming the dielectric liner includes forming a dielectric protrusion extending laterally into the gate conductor. 2. The method of claim 1, wherein forming the gate conductor comprises: filling the cavity within the dielectric liner with an initial gate conductor extending above the substrate upper surface;removing an upper part of the initial gate conductor leaving behind an initial first gate conductor portion of the initial gate conductor having an initial upper gate conductor surface lying at a third depth below the substrate upper surface and leaving behind an upper sidewall portion of the initial gate conductor proximate an initial upper liner portion;converting an upper part of the first gate portion to a temporary dielectric region of temporary thickness and converting the upper sidewall portion to a further dielectric region on the initial upper liner portion, leaving a first gate portion of the initial gate conductor in the cavity, wherein the first gate portion has an upper gate conductor surface lying at a fourth depth below the upper substrate surface;anisotropically removing the temporary dielectric region and part of the further dielectric region, substantially exposing the upper gate conductor surface and providing the upper liner thickness of the dielectric liner in the upper liner portion; andcovering the upper surface of the first gate portion with the second gate portion and the third gate portion having a fourth upper surface separated from the upper substrate surface by the gate extension distance, the combination of the first gate portion, the second gate portion and the third gate portion forming the gate conductor of the MOSFET. 3. The method of claim 1, wherein the gate conductor has a first lateral cross-sectional width proximate the upper liner portion and a larger second lateral cross-sectional width proximate the lower liner portion. 4. The method of claim 1, wherein forming the final source regions comprises: forming initial source regions of the first conductivity type, occupying an initial volume within the body regions; andcounter doping a portion of the initial source regions with impurities of the second, opposite conductivity type, thereby providing the final source regions occupying a smaller volume within the body regions than the initial source regions. 5. The method of claim 4, wherein counter doping of the initial source regions occurs, at least in part, in locations away from the dielectric liner so that the final source regions lie proximate the upper sidewall portion. 6. The method of claim 1, wherein the dielectric protrusion is located proximate the lower source extremity. 7. The method of claim 1, wherein the dielectric protrusion is located approximately at an intersection of the lower liner portion and the upper liner portion. 8. A method for forming a power MOSFET having final source region, drain region and contact and gate conductor, comprising: providing a semiconductor containing substrate of a first conductivity type having a first upper surface;forming above the first upper surface a first dielectric region having a lower boundary at a first depth below the first surface, the lower boundary coupled to the first surface by an initial upper sidewall region with an initial curved shape;excavating a passage of a first width extending through the first dielectric region to the lower boundary;forming a cavity in the substrate beneath the lower boundary and having a second depth beneath the first upper surface and a second width larger than the first width, the cavity having a bottom and sidewall region, wherein the sidewall region is coupled to the first upper surface by the initial curved shape;providing a dielectric liner covering the bottom lower sidewall and curved region of the cavity in the substrate, the dielectric liner having a first thickness on the bottom and a lower sidewall of the cavity and an initial second thickness proximate the curved shape at least partly greater than the first thickness;filling the cavity within the dielectric liner with an initial gate conductor extending above the first upper surface of the substrate;removing an upper part of the initial gate conductor leaving behind a first portion of the initial gate conductor having a second upper surface lying at a third depth below the first surface of the substrate and leaving behind an upper sidewall portion of the initial gate conductor proximate the curved region;converting an upper part of the first portion to a second dielectric region of third thickness and converting the upper sidewall portion to a third dielectric region, leaving behind within the cavity a residual portion of the initial gate conductor, wherein the residual portion has a third upper surface lying at a fourth depth below the first upper surface of the substrate;substantially anisotropically removing the second dielectric region and part of the third dielectric region, thereby substantially exposing the third upper surface of the residual portion and providing a greater lateral thickness of the dielectric liner proximate the curved region of the substrate;covering the third upper surface of the residual portion with a further gate conductor having a fourth upper surface located a first distance from the surface of the substrate, which with the residual portion form the gate conductor of the MOSFET, wherein the further gate conductor is laterally separated from the substrate at least in part by an upper portion of the dielectric liner;forming a body region of a second, opposite, conductivity type, extending into the substrate by body region distance from substrate surface, and located laterally proximate the gate conductor but separated therefrom by the dielectric liner;forming a source region of the first conductivity type in the body region proximate the upper portion of the dielectric liner and extending to a fifth depth from the substrate surface less than the body region distance; andproviding a source lead overlying and insulated from the gate conductor and in Ohmic contact at least with the source region, andwherein providing the dielectric liner includes forming a dielectric protrusion extending laterally into the gate conductor. 9. The method of claim 8, wherein forming the source region comprises: forming an initial source region of the first conductivity type, occupying an initial volume within the body region; andcounter doping a portion of the initial source region with impurities of the second, opposite conductivity type, thereby providing the source region occupying a smaller volume within the body region than the initial source region. 10. The method of claim 8, wherein forming the dielectric protrusion comprises forming the dielectric protrusion approximately at the intersection of the upper portion of the dielectric liner and a thinner lower portion of the dielectric liner.
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Zambrano Raffaele (Catania ITX) Blanchard Richard A. (Los Altos CA), Integrated structure current sensing resistor for power devices particularly for overload self-protected power MOS devic.
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