IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0586815
(2012-08-15)
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등록번호 |
US-8946669
(2015-02-03)
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발명자
/ 주소 |
- Jo, Sung Hyun
- Kim, Kuk-Hwan
- Kumar, Tanmay
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출원인 / 주소 |
|
대리인 / 주소 |
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인용정보 |
피인용 횟수 :
1 인용 특허 :
113 |
초록
▼
A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the l
A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.
대표청구항
▼
1. A method for forming a resistive memory device comprising: providing a substrate comprising a first metal material;forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein
1. A method for forming a resistive memory device comprising: providing a substrate comprising a first metal material;forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material;forming an amorphous layer from the upper region of the conductive silicon-bearing layer; anddisposing an active metal material above the amorphous layer. 2. The method of claim 1wherein a barrier layer is formed on the amorphous layer prior to the disposing the active metal material above the amorphous layer; andwherein the barrier layer comprises a nitride layer. 3. The method of claim 1 wherein the barrier layer has a thickness within the range of approximately 20 Angstroms to approximately 50 Angstroms. 4. The method of claim 1wherein the active metal material comprises a metal selected from a group consisting of: aluminum, silver, platinum, palladium, copper, and nickel. 5. The method of claim 1 wherein forming the amorphous layer from the upper region comprises: performing an Argon, silicon, and/or oxygen plasma etch on an exposed surface of the conductive silicon-bearing layer. 6. The method of claim 1wherein forming the amorphous layer from the upper region comprises: performing an Argon plasma etch on an exposed surface of the conductive silicon-bearing layer; andwherein the plasma etch comprises a bias power within a range of approximately 30 watts to approximately 120 watts. 7. The method of claim 1wherein forming the amorphous layer from the upper region comprises: performing an ion implantation on the upper region of the conductive silicon-bearing; andwherein an ion for the ion implant is selected from a group consisting: Argon, silicon, and oxygen. 8. The method of claim 1 wherein the amorphous layer has a thickness within the range of approximately 2 to approximately 10 nanometers. 9. The method of claim 1 wherein the amorphous layer has a thickness within the range of approximately 30 Angstroms to approximately 40 Angstroms. 10. The method of claim 1wherein the conductive silicon-bearing layer comprises SixGex-1;wherein the conductive silicon-bearing layer comprises a p-type dopant; andwherein the amorphous layer comprises a silicon oxide. 11. A method for fabricating a device comprising: providing a substrate including a plurality of CMOS devices;forming a resistive memory upon the substrate comprising:forming a first metal material;forming a monolithic conductive silicon-bearing layer on top of the first metal material;forming an amorphous silicon and oxygen-bearing layer in a portion of the monolithic conductive silicon-bearing layer; anddisposing an active metal material above the amorphous silicon and oxygen-bearing layer; andcoupling the resistive memory to at least one of the plurality of CMOS devices. 12. The method of claim 11 further comprising after the forming the amorphous silicon and oxygen-bearing layer, forming a barrier layer on the portion of the monolithic conductive silicon-bearing layer, prior to the disposing the active metal material. 13. The method of claim 11 wherein the barrier layer is selected from a group of materials consisting of: a nitride, an oxide, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, or tungsten nitride. 14. The method of claim 11wherein the active metal material comprises a metal selected from a group consisting of: aluminum, silver, platinum, palladium, copper, and nickel. 15. The method of claim 11 wherein the forming the amorphous layer from the upper region comprises an etch on an exposed surface of the monolithic conductive silicon-bearing layer, wherein the etch includes a material selected from a group consisting of: argon, silicon, oxygen. 16. The method of claim 11wherein the forming the amorphous silicon and oxygen-bearing layer comprises: performing an Argon plasma etch on an exposed surface of the monolithic conductive silicon-bearing layer using a bias power within a range of approximately 30 watts to approximately 120 watts. 17. The method of claim 11wherein the forming the amorphous silicon and oxygen-bearing layer comprises: performing an ion implantation on an exposed surface of the monolithic conductive silicon-bearing layer; andwherein an ion for the ion implantation is selected from a group consisting: argon, silicon, and oxygen. 18. The method of claim 11 wherein the amorphous silicon and oxygen-bearing layer has a thickness within the range of approximately 2 to approximately 10 nanometers. 19. The method of claim 11 wherein the amorphous silicon and oxygen-bearing layer has a thickness within the range of approximately 30 Angstroms to approximately 40 Angstroms. 20. The method of claim 11wherein the monolithic conductive silicon-bearing layer comprises a p-doped SixGex-1; andwherein the amorphous silicon and oxygen-bearing layer comprises SixGeyOz (x, y, z integers. 21. A method for forming a resistive memory device comprising: providing a substrate comprising a first metal material;forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material;forming an amorphous layer from the upper region of the conductive silicon-bearing layer, wherein forming the amorphous layer from the upper region comprises a process selected from a group consisting of:performing an Argon, silicon, and/or oxygen plasma etch on an exposed surface of the conductive silicon-bearing layer; andperforming an ion implantation on the upper region of the conductive silicon-bearing, and wherein an ion for the ion implant is selected from a group consisting: Argon, silicon, and oxygen; anddisposing an active metal material above the amorphous layer. 22. The method of claim 21wherein a barrier layer is formed on the amorphous layer prior to the disposing the active metal material above the amorphous layer; andwherein the barrier layer comprises a nitride layer. 23. The method of claim 21 wherein the barrier layer has a thickness within the range of approximately 20 Angstroms to approximately 50 Angstroms. 24. The method of claim 21wherein the active metal material comprises a metal selected from a group consisting of: aluminum, silver, platinum, palladium, copper, and nickel. 25. The method of claim 21 wherein the amorphous layer has a thickness within the range of approximately 2 to approximately 10 nanometers. 26. The method of claim 21 wherein the amorphous layer has a thickness within the range of approximately 30 Angstroms to approximately 40 Angstroms. 27. The method of claim 21wherein the conductive silicon-bearing layer comprises polycrystalline silicon and germanium. 28. The method of claim 21 wherein the amorphous layer comprises SiOx. 29. The method of claim 21 further comprising forming a barrier layer on top of the active metal layer, wherein a material for the barrier layer is selected from a group consisting of: titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and tungsten nitride. 30. The method of claim 21 wherein a thickness of the upper region of the conductive silicon-bearing layer is less than a thickness of the lower region of the conductive silicon-bearing layer.
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