Method and device for generating an adjustable bandgap reference voltage
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G05F-003/16
G05F-003/20
G05F-003/30
출원번호
US-0472731
(2012-05-16)
등록번호
US-8947069
(2015-02-03)
발명자
/ 주소
Fort, Jimmy
Soude, Thierry
출원인 / 주소
STMicroelectronics (Rousset) SAS
대리인 / 주소
Slater & Matsil, L.L.P.
인용정보
피인용 횟수 :
1인용 특허 :
10
초록▼
According to an embodiment, generating an adjustable bandgap reference voltage includes generating a current proportional to absolute temperature (PTAT). Generating the PTAT current includes equalizing voltages across the terminals of a core that is designed to be traversed by the PTAT current. Gene
According to an embodiment, generating an adjustable bandgap reference voltage includes generating a current proportional to absolute temperature (PTAT). Generating the PTAT current includes equalizing voltages across the terminals of a core that is designed to be traversed by the PTAT current. Generating the adjustable bandgap reference also includes generating a current inversely proportional to absolute temperature (CTAT), summing the PTAT and the CTAT currents and generating the bandgap reference voltage based on the sum of the currents. Equalizing includes connecting-across the terminals of the core a first fed-back amplifier with at least one first stage arranged as a folded setup and including first PMOS transistors arranged according to a common-gate setup. Equalizing also includes biasing the first stage based on the CTAT current. The summation of the PTAT and CTAT currents is performed in the feedback stage of the first amplifier.
대표청구항▼
1. A method for generating an adjustable bandgap reference voltage, comprising: generating a current proportional to absolute temperature, by equalizing a voltage across terminals of a core, the core configured to then be traversed by the current proportional to absolute temperature;generating a cur
1. A method for generating an adjustable bandgap reference voltage, comprising: generating a current proportional to absolute temperature, by equalizing a voltage across terminals of a core, the core configured to then be traversed by the current proportional to absolute temperature;generating a current inversely proportional to absolute temperature;summing the current proportional to absolute temperature and the current inversely proportional to absolute temperature; andgenerating the bandgap reference voltage on the basis of the sum of currents,wherein the equalizing comprises connecting a first fed-back amplifier across the terminals of the core, the first fed-back amplifier having a first stage comprising first PMOS transistors having conduction paths between the terminals of the core and a reference terminal and having a common-gate connection, the equalizing further comprising biasing the first stage on the basis of the current inversely proportional to absolute temperature;wherein the summing is performed in a feedback stage of the first fed-back amplifier;wherein the current inversely proportional to absolute temperature is generated by using a second fed-back amplifier having a first stage having a part common with the first stage of the first fed-back amplifier and wherein the first stage of the second fed-back amplifier is also biased on the basis of the current inversely proportional to absolute temperature; andwherein the first stage of the first fed-back amplifier and the first stage of the second fed-back amplifier are biased with the current inversely proportional to absolute temperature or with a fraction of the current inversely proportional to absolute temperature. 2. A device for generating an adjustable bandgap reference voltage, the device comprising: first means for generating a current proportional to absolute temperature, the first means comprising first processing means connected to terminals of a core and designed to equalize the voltages across the terminals of the core;second means for generating a current inversely proportional to absolute temperature connected to the core; andan output module designed to generate the reference voltage,wherein the first processing means comprise a first amplifier possessing at least one first stage, biased on the basis of the current inversely proportional to absolute temperature, arranged according to a folded setup and comprising first PMOS transistors arranged according to a common-gate setup, and a feedback stage whose input is connected to the output of the first amplifier and whose output is connected to the input of the first stage as well as to at least one terminal of the core, the feedback stage being intended to be traversed by an intermediate current equal to the sum of the current proportional to absolute temperature and of the current inversely proportional to absolute temperature,wherein the output module is connected to the feedback stage,wherein the second generating means comprise a follower amplifier setup connected to a terminal of the core, wherein the follower amplifier setup comprises a second amplifier having a first stage, also biased on the basis of the current inversely proportional to absolute temperature, comprising second PMOS transistors arranged according to a common-gate setup, the first stage of the second amplifier having a part common with the first stage of the first amplifier, and a feedback transistor connected between the output of the second amplifier and an input of the second amplifier, andwherein the first stage of the first amplifier comprises at least one differential pair of branches connected between the two terminals of the core and a reference voltage, the first stage of the second amplifier comprises at least one differential pair of branches having a branch in common with the at least one differential pair of branches of the first stage of the first amplifier, and the second generating means furthermore comprise a first resistive circuit connected in series with the feedback transistor, the first stage of the first amplifier comprises within a differential pair of branches, a pair of first NMOS bias transistors connected in series with a pair of first PMOS transistors, the first stage of the second amplifier comprises within a differential pair of branches, a pair of second NMOS bias transistors connected in series with a pair of second PMOS transistors. 3. The device according to claim 2, wherein the first amplifier is a differential-input single-output amplifier and the feedback stage is a single-input differential-output feedback stage. 4. The device according to claim 2, wherein a bias loop is connected between the second generating means and the respective first stages of the first amplifier and of the second amplifier, and is designed to bias each of these first stages on the basis of the current inversely proportional to absolute temperature. 5. The device according to claim 4, wherein the bias loop comprises the feedback transistor, a first additional transistor forming, with the feedback transistor, first current-copying means, and the pair of first NMOS bias transistors, and is designed to cause a flow, in each branch, of a bias current equal to the current inversely proportional to absolute temperature or to a fraction of this current inversely proportional to absolute temperature. 6. The device according to claim 5, wherein the feedback stage comprises a pair of third PMOS transistors mutually connected by their gate, wherein respective sources of the third PMOS transistors are connected to a power supply terminal, respective drains of the third PMOS transistors are linked to the two terminals of the core, and the output module comprising a second resistive circuit comprising a second additional PMOS transistor forming, with the third PMOS transistors of the feedback stage, second copying means configured to deliver, in the second resistive circuit, a copied current equal to the intermediate current or a multiple or sub-multiple of the intermediate current. 7. The device according to claim 6, further comprising a first auxiliary transistor forming with the first additional transistor a first cascode setup and at least one second auxiliary transistor forming with the second additional PMOS transistor of the second resistive circuit a second cascode setup. 8. The device according to claim 5, wherein the first stage of the first amplifier comprises a differential pair of branches connected in a crossed manner between the two terminals of the core and the reference voltage as well as first pseudo-current mirrors, the first stage of the second amplifier comprises a differential pair of branches connected in a crossed manner between on the one hand a terminal of the core and the output of the feedback transistor and on the other hand the reference voltage as well as second pseudo-current mirrors, and the first processing means comprise a dummy branch connected to the bias loop so that the numbers of branches respectively connected to the two terminals of the core are equal. 9. The device according to claim 2, wherein the first amplifier comprises an inverter stage arranged in a setup of the common-source type, and connected between the output of the first stage and the input of the feedback stage, the output of the inverter stage forming the output of the amplifier and the second amplifier comprises an inverter stage arranged in a setup of the common-source type, connected between the output of the first stage and a gate of the feedback transistor. 10. A device for generating an adjustable bandgap reference voltage, comprising: first means for generating a current proportional to absolute temperature comprising first processing means connected to terminals of a core and designed to equalize the voltages across the terminals of the core;second means for generating a current inversely proportional to absolute temperature connected to the core, wherein the second means comprise a second amplifier including at least one first stage and a feedback transistor; andan output module designed to generate the reference voltage,wherein the first processing means comprise a first amplifier including at least one first stage, biased on the basis of the current inversely proportional to absolute temperature, arranged according to a folded setup and comprising first PMOS transistors arranged according to a common-gate setup, anda feedback stage whose input is connected to the output of the first amplifier and whose output is connected to the input of the first stage as well as to at least one terminal of the core, the feedback stage being intended to be traversed by an intermediate current equal to the sum of the current proportional to absolute temperature and of the current inversely proportional to absolute temperature, andwherein the output module is connected to the feedback stage,wherein the first amplifier comprises an inverter stage arranged in a setup of the common-source type, and connected between the output of the first stage and the input of the feedback stage, the output of the inverter stage forming the output of the first amplifier, andthe second amplifier comprises an inverter stage arranged in a setup of the common-source type, connected between the output of the first stage and the gate of the feedback transistor, andwherein the first stage of the first amplifier comprises a differential pair of branches connected in a crossed manner between two terminals of the core and the reference voltage as well as first pseudo-current mirrors,the first stage of the second amplifier comprises a differential pair of branches connected in a crossed manner between on the one hand a terminal of the core and the output of the feedback transistor and on the other hand the reference voltage as well as second pseudo-current mirrors, andthe first processing means comprise a dummy branch connected to a bias loop so that the numbers of branches respectively connected to the two terminals of the core are equal, and wherein the inverter stage of the first amplifier and the inverter stage of the second amplifier respectively comprise two distinct current-copying means, each current-copying means being connected to two branches of the corresponding first stage by two current mirrors. 11. An integrated circuit comprising: a power supply terminal;a ground terminal;a first circuit configured to generate a current proportional to absolute temperature, the first circuit including a first processing circuit connected to terminals of a core circuit and configured to equalize voltage across the terminals of the core circuit, the first processing circuit including a first amplifier having a first stage, biased on the basis of the current inversely proportional to absolute temperature, comprising first PMOS transistors having conduction paths between the terminals of the core circuit and the ground terminal and having a common-gate connection, and a feedback stage having an input connected to an output of the first amplifier and having an output connected to the input of the first stage and to a terminal of the core, the feedback stage being configured to be traversed by an intermediate current equal to the sum of the current proportional to absolute temperature and of the current inversely proportional to absolute temperature;a second circuit configured to generate a current inversely proportional to absolute temperature, and being connected to the core, wherein the second circuit includes a follower amplifier setup connected to a terminal of the core, and wherein the follower amplifier setup comprises a second amplifier having a first stage, also biased on the basis of the current inversely proportional to absolute temperature, the second amplifier comprising second PMOS transistors arranged according to a common-gate setup, the first stage of the second amplifier having a part common with the first stage of the first amplifier, anda feedback transistor connected between the output of the second amplifier and an input of the second amplifier;an output module connected to the feedback stage and configured to output a reference voltage; andwherein a bias loop is connected between the second circuit and the respective first stages of the first amplifier and of the second amplifier, and is designed to bias each of these first stages on the basis of the current inversely proportional to absolute temperature. 12. The integrated circuit according to claim 11, further comprising a logic circuit configured to receive the reference voltage output by the output module. 13. The integrated circuit according to claim 11, wherein the first amplifier is a differential-input single-output amplifier and the feedback stage is a single-input differential-output feedback stage.
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이 특허에 인용된 특허 (10)
Can Sumer, Bandgap reference voltage circuit with PTAT current source.
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