The disclosure concerns circuitry for controlling a power transistor of a drive circuit arranged to drive an electrical component, the circuitry comprising: a variable current source adapted to set the level of a current for charging a control terminal of said power transistor; and a control circuit
The disclosure concerns circuitry for controlling a power transistor of a drive circuit arranged to drive an electrical component, the circuitry comprising: a variable current source adapted to set the level of a current for charging a control terminal of said power transistor; and a control circuit adapted to control said variable current source in a continuous manner based on a feedback voltage.
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1. Circuitry for controlling a power transistor of a drive circuit arranged to drive an electrical component, the circuitry comprising: a variable current source configured to set a level of a charging current for charging a control terminal of said power transistor;a control circuit configured to c
1. Circuitry for controlling a power transistor of a drive circuit arranged to drive an electrical component, the circuitry comprising: a variable current source configured to set a level of a charging current for charging a control terminal of said power transistor;a control circuit configured to control said variable current source with a non-discrete, continuous first control signal based on a feedback voltage, wherein said variable current source is configured to set, based on the first control signal, both the level of said current for charging said control terminal of said power transistor and a level of a current for discharging said control terminal of said power transistor;a first current mirror arranged to supply said charging current for charging said control terminal of said power transistor based on the current through said variable current source;a second current mirror arranged to supply said discharging current for discharging said control terminal of said power transistor based on the current through said variable current source;a first switch configured to supply the charging current from the first current mirror to the control terminal of said power transistor in response to a second control signal having a first level; anda second switch configured to supply the discharging current from the control terminal of said power transistor to the second current mirror in response to the second control signal having a second level. 2. The circuitry of claim 1, wherein said variable current source is configured to generate a monotonically increasing current for charging said control terminal, under control of the control circuit. 3. The circuitry of claim 1, wherein said control circuit is configured to cause said variable current source to generate a monotonically decreasing current for discharging said control terminal. 4. The circuitry of claim 1, wherein said variable current source includes a transistor having a control terminal coupled to receive a control signal from said control circuit, and a fixed current source coupled in parallel with said transistor. 5. The circuitry of claim 1, wherein said control circuit comprises at least one resistor arranged to convert said feedback voltage into a feedback current level, and a third current mirror configured to set the level of current through the variable current source based on said feedback current level. 6. The circuitry of claim 1, wherein said control circuit comprises an operational amplifier configured to provide an output signal proportional to said feedback voltage. 7. The circuitry of claim 1, wherein said feedback voltage is one of: a voltage level supplied by said power transistor; anda voltage at the control terminal of said power transistor. 8. The circuitry of claim 1, wherein said current for charging the control terminal of said power transistor is equal to I_START+L(VREF), where I_START is a constant starting current value, L is a constant and VREF is a voltage level equal to said feedback voltage or proportional to said feedback voltage. 9. The circuitry of claim 1, wherein the first and second switches are arranged to respectively control the charging and discharging of said control terminal of said power transistor based on the second control signal, which is a pulse width modulation signal. 10. The circuitry of claim 1, wherein: the first current mirror includes first, second and third legs, the first leg including the current source coupled between first and second supply nodes and the third leg including the first switch coupled between the first supply node and an output node configured to be coupled to the control terminal of the power transistor; andthe second current mirror includes first and second legs, the first leg of the second current mirror including a transistor coupled by the second leg of the first current mirror and a feedback node configured to receive the feedback voltage and the second leg of the second current mirror including the second switch which is coupled between the feedback node and the output node. 11. A drive circuit, comprising: a power transistor configured to drive a load and having a gate terminal;circuitry configured to control the power transistor, the circuitry including: a variable current source having a terminal electrically coupled to the gate terminal of the power transistor and configured to set a level of a charging current that charges the gate terminal of said power transistor;a control circuit configured to control said variable current source with a non-discrete, continuous first control signal based on a feedback voltage, wherein said variable current source is configured to set, based on the first control signal, both the level of said charging current and a level of a discharging current that discharges said gate terminal of said power transistor;a first current mirror arranged to supply said charging current that charges said gate terminal of said power transistor based on the current through said variable current source, anda second current mirror arranged to supply said discharging current that discharges said gate terminal of said power transistor based on the current through said variable current source. 12. The drive circuit of claim 11, wherein: the first current mirror includes a first leg coupled between a supply node and the variable current source, a second leg coupled to the supply node, and a third leg coupled between the supply node and the gate terminal of the power transistor; andthe second current mirror includes a first leg coupled between an output terminal of the power transistor and the second leg of the first current mirror and a second leg coupled between the output and gate terminals of the power transistor. 13. The drive circuit of claim 12, wherein the third leg of the first current mirror includes a first control transistor and the second leg of the second current mirror includes a second control transistor, the first control transistor being configured to supply the charging current from the first current mirror to the gate terminal of said power transistor in response to a second control signal having a first level, and the second control transistor being configured to supply the discharging current from the gate terminal of said power transistor to the second current mirror in response to the second control signal having a second level. 14. The drive circuit of claim 11, wherein said control circuit comprises at least one resistor arranged to convert said feedback voltage into a feedback current level, and a current mirror configured to set the level of current through the variable current source based on said feedback current level. 15. The drive circuit of claim 11, wherein said variable current source is configured to generate a monotonically increasing current for charging said gate terminal, under control of the control circuit. 16. An electronic circuit comprising: a pulse width modulation (PWM) signal generator configured to provide a PWM signal; anda drive circuit configured to drive a load based on the PWM signal generated by said generator, the drive circuit including:a power transistor configured to drive the load and having a gate terminal;circuitry configured to control the power transistor, the circuitry including: a variable current source having a terminal electrically coupled to the gate terminal of the power transistors and configured to set a level of a charging current that charges the gate terminal of said power transistor;a control circuit configured to control said variable current source with a non-discrete continuous signal based on a feedback voltage; andfirst and second switches arranged to control the charging and discharging of said gate terminal of said power transistor based on the PWM signal, wherein said variable current source is configured to set, based on the non-discrete continuous signal, both the level of said charging current and a level of a discharging current that discharges said gate terminal of said power transistor, the first switch being configured to supply the charging current to the gate terminal of said power transistor in response to the PWM signal having a first level, and the second switch being configured to supply the discharging current from the gate terminal of said power transistor in response to the PWM signal having a second level; anda first current mirror arranged to supply said charging current for charging said gate terminal of said power transistor based on the current through said variable current source, and a second current mirror arranged to supply the discharging current for discharging said gate terminal of said power transistor based on the current through said variable current source. 17. The electronic circuit of claim 16, wherein: the first current mirror includes a first leg coupled between a supply node and the variable current source, a second leg coupled to the supply node, and a third leg coupled between the supply node and the gate terminal of the power transistor; andthe second current mirror includes a first leg coupled between an output terminal of the power transistor and the second leg of the first current mirror and a second leg coupled between the output and gate terminals of the power transistor. 18. The electronic circuit of claim 17, wherein the third leg of the first current mirror includes the first switch and the second leg of the second current mirror includes the second switch. 19. The electronic circuit of claim 16, wherein said control circuit comprises at least one resistor arranged to convert said feedback voltage into a feedback current level, and a current mirror configured to set the level of current through the variable current source based on said feedback current level. 20. The electronic circuit of claim 16, wherein said variable current source is configured to generate a monotonically increasing current for charging said gate terminal, under control of the control circuit. 21. A method, comprising: controlling a power transistor of a drive circuit to drive an electrical component, the controlling including: setting, by a variable current source, a level of a charging current and using the charging current to charge a gate terminal of said power transistor; andcontrolling said variable current source with a non-discrete continuous signal based on a feedback voltage; andsetting, by the variable current source, a level of a discharging current for discharging said gate terminal of said power transistor, wherein setting the level of the charging current for charging said gate terminal and setting the level of the discharging current for discharging said gate terminal are each performed in response to the same non-discrete continuous control signal, wherein:setting, by the variable current source, the level of the charging current includes producing the charging current by mirroring a current provided by the variable current source;using the charging current to charge the gate terminal of said power transistor includes providing the charging current through a first control switch to the gate terminal in response to a control terminal of the first control switch being controlled by a control signal at a first level;setting, by the variable current source, the level of the discharging current includes producing the discharging current by mirroring the current provided by the variable current source; anddischarging said gate terminal of said power transistor by providing the discharge current from the gate terminal through a second control switch in response to a control terminal of the second control switch being controlled by the control signal at second level. 22. The method of claim 21, wherein the controlling includes causing said variable current source to generate a monotonically increasing current for charging said gate terminal. 23. The method of claim 21, wherein the controlling includes causing said variable current source to generate a monotonically decreasing current for discharging said gate terminal.
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이 특허에 인용된 특허 (10)
Matsuki, Fumirou, Buffer circuit with reduced power consumption.
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