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A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the

A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

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1. A manufacturing process for preparing a semiconductor on insulator (SeOI) structure that exhibits type-reduced electrical losses, the substrate successively comprising a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and having a polycrystalline sili

1. A manufacturing process for preparing a semiconductor on insulator (SeOI) structure that exhibits type-reduced electrical losses, the substrate successively comprising a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and having a polycrystalline silicon layer interleaved between the support substrate and the oxide layer, which process comprises: oxidizing a donor substrate made of semiconductor material to form an oxide layer on a surface thereof;implanting ions in the donor substrate to form an embrittlement zone therein;depositing a semiconductive decoupling layer on a support substrate, the semiconductive decoupling layer having a mesh parameter different from a mesh parameter of the support substrate;after depositing the semiconductive decoupling layer, depositing a polycrystalline silicon layer on the semiconductive decoupling layer;bonding the donor substrate and the support substrate together with the oxide layer being located therebetween at a bonding interface, the support substrate having a high resistivity that is greater than 500 Ω·cm, and the polycrystalline silicon layer on an upper face of the support substrate which is bonded to the donor substrate;fracturing the donor substrate at the embrittlement zone to transfer to the support substrate the thin layer of semiconductor material from the donor substrate and form the SeOI structure; andconducting at least one thermal stabilization of the SeOI structure, at a temperature not exceeding 950° C., and for a time of at least 10 minutes. 2. The process of claim 1, wherein the resistivity of the support substrate is greater than 1,000 Ω·cm and is obtained by a thermal treatment carried out prior to the deposition of the polycrystalline silicon layer thereon. 3. The process of claim 2, wherein the thermal treatment comprises heating to a temperature of between 500 and 1,200° C. for 30 minutes to 20 hours. 4. The process of claim 2, wherein the thermal treatment is an annealing treatment conducted over multiple steps, with the steps including heating to different temperatures. 5. The process of claim 4, wherein the multiple steps comprise three steps conducted respectively at three different temperatures. 6. The process of claim 1, wherein the at least one thermal stabilization is carried out for several hours. 7. The process of claim 1, further comprising a rapid thermal treatment carried out over a period of less than 10 minutes and at a temperature greater than 1,000° C. 8. The process of claim 1, wherein the thermal stabilization comprises at least one thermal stabilization treatment and one thermal thinning treatment of the thin layer. 9. The process of claim 1, wherein the decoupling layer contains comprises polycrystalline silicon. 10. The process of claim 9, wherein the semiconductive decoupling layer also contains another atomic species-based semiconductor material. 11. The process of claim 10, wherein the depositing of the semiconductive decoupling layer and the depositing of the polycrystalline silicon layer are carried out continuously, by a simultaneous feed from at least two gas sources, one of which is a source for polycrystalline silicon and the other of which is a source for the other atomic species, then by feed only from the source for polycrystalline silicon. 12. The process of claim 1, wherein the semiconductive decoupling layer is SiC or SiGe. 13. The process of claim 1, which further comprises depositing a further decoupling layer on the polycrystalline silicon layer. 14. The process of claim 13, further comprising depositing at least one stack constituted by a polycrystalline silicon layer and a decoupling layer on the further decoupling layer. 15. The process of claim 1, wherein the support substrate has a resistivity that is greater than 1,000 Ω·cm and the polycrystalline silicon layer has a resistivity that is greater than 10,000 Ohms·cm. 16. The process of claim 1, wherein the semiconductive decoupling layer contains polycrystalline silicon and another atomic species-based semiconductor material.