IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0925025
(2013-06-24)
|
등록번호 |
US-8963455
(2015-02-24)
|
우선권정보 |
JP-2012-160375 (2012-07-19) |
발명자
/ 주소 |
- Kurosawa, Minoru
- Matsuya, Yuki
|
출원인 / 주소 |
- Renesas Electronics Corporation
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
3 |
초록
▼
When a motor drive control device is integrated in a semiconductor integrated circuit having a small chip area, calibration for improving the accuracy of detection of a counter electromotive voltage, which is for detecting the speed of a motor, is enabled. A first multiplier performs multiplication
When a motor drive control device is integrated in a semiconductor integrated circuit having a small chip area, calibration for improving the accuracy of detection of a counter electromotive voltage, which is for detecting the speed of a motor, is enabled. A first multiplier performs multiplication between a drive current detection signal and first gain information in a first register. A subtractor performs subtraction between a drive voltage command signal and a first multiplication result in the first multiplier. A second multiplier performs multiplication between a subtraction result in the subtractor and second gain information in a second register to generate counter electromotive voltage information as information on a second multiplication result. The drive voltage command signal in a control unit is set to a predetermined value to generate a condition which maintains the speed of the motor and a counter electromotive voltage at substantially zero.
대표청구항
▼
1. A motor drive control device, comprising: a digital control unit;a digital/analog converter;a driver output unit;a drive current detection amplifier;an analog/digital converter; anda counter electromotive voltage detection unit,wherein, to an output terminal of the driver output unit, a series co
1. A motor drive control device, comprising: a digital control unit;a digital/analog converter;a driver output unit;a drive current detection amplifier;an analog/digital converter; anda counter electromotive voltage detection unit,wherein, to an output terminal of the driver output unit, a series coupling between a motor and a detection resistor is allowed to be coupled,wherein the digital control unit generates and supplies a digital drive voltage command signal to an input terminal of the digital/analog converter,wherein the digital/analog converter responds to the digital drive voltage command signal generated from the digital control unit to generate an analog drive voltage command signal,wherein the driver output unit responds to the analog drive voltage command signal generated from the digital/analog converter to generate a drive output signal for driving the series coupling between the motor and the detection resistor,wherein the drive current detection amplifier responds to a drive current flowing in the detection resistor to generate a drive current analog amplified signal,wherein the analog/digital converter responds to the drive current analog amplified signal generated from the drive current detection amplifier to generate a digital drive current detection signal,wherein the counter electromotive voltage detection unit includes a first digital multiplier, a digital subtractor, a second digital multiplier, a first register, and a second register,wherein the first digital multiplier performs multiplication between the digital drive current detection signal generated from the analog/digital converter and first gain information stored in the first register to generate a first multiplication result,wherein the digital subtractor performs subtraction between the digital drive voltage command signal generated from the digital control unit and the first multiplication result generated from the first digital multiplier to generate a subtraction result N,wherein the second digital multiplier performs multiplication between the subtraction result generated from the digital subtractor and second gain information stored in the second register to generate digital counter electromotive voltage information as information on a second multiplication result,wherein the digital drive voltage command signal generated from the digital control unit is set to a predetermined value to allow a condition which maintains a speed of the motor and a counter electromotive voltage at substantially zero to be generated, andwherein, under the condition, the first gain information which sets a value of the digital counter electromotive voltage information generated from the second digital multiplier to substantially zero is allowed to be stored in the first register. 2. A motor drive control device according to claim 1, wherein, according to a predetermined search algorithm, the first gain information which sets the value of the digital counter electromotive voltage information to substantially zero is allowed to be stored in the first register. 3. A motor drive control device according to claim 2, wherein the predetermined search algorithm is a binary search. 4. A motor drive control device according to claim 1, wherein the digital control unit includes a digital subtraction circuit and a clamp circuit,wherein the digital subtraction circuit generates difference information on a difference between a digital drive current command value supplied from the outside and the digital drive current detection signal generated from the analog/digital converter,wherein the clamp circuit responds to the difference information generated from the digital subtraction circuit to generate the digital drive voltage command signal, andwherein, when the digital drive voltage command signal is generated, the clamp circuit respectively clamps an increase and a decrease in the digital drive voltage command signal due to a decrease in a variation in the drive current resulting from a change in the digital drive current command value to a predetermined maximum value and a predetermined minimum value. 5. A motor drive control device according to claim 4, wherein the driver output unit implements a pulse drive operation mode under PWM control in which, in response to a PWM carrier signal generated from a PWM modulator, the drive output signal is generated,wherein the counter electromotive voltage detection unit further includes a digital filter coupled to an output terminal of the second digital multiplier, andwherein the digital filter functions as a PWM carrier ripple removal filter for generating a digital counter electromotive voltage signal in which a ripple component of the PWM carrier signal included in the digital counter electromotive voltage information generated from the output terminal of the second digital multiplier is suppressed in a predetermined amount of attenuation. 6. A motor drive control device according to claim 5, wherein the digital filter functioning as the PWM carrier ripple removal filter includes a digital lowpass filter, a down-sampler, and a sampling pulse generator,wherein, to an input terminal of the digital lowpass filter, the digital counter electromotive voltage information is supplied, while an output terminal of the digital lowpass filter is coupled to an input terminal of the down-sampler,wherein, to an input terminal of the sampling pulse generator, a PWM clock signal as a base signal for generating the PWM carrier signal is supplied from the PWM modulator to cause the sampling pulse generator to generate a sampling clock in synchronization with the PWM clock signal, andwherein, to a sampling control terminal of the down-sampler, the sampling clock generated from the sampling pulse generator is supplied to cause the digital counter electromotive voltage signal to be generated from an output terminal of the down-sampler. 7. A motor drive control device according to claim 6, wherein the digital lowpass filter of the digital filter includes a moving average filter for generating a digital lowpass output signal by averaging a plurality of input data items supplied in time series. 8. A motor drive control device according to claim 5, wherein the driver output unit includes a pre-driver, a first driver output amplifier, and a second driver output amplifier,wherein, to an input terminal of the pre-driver, the analog drive voltage command signal generated from the digital/analog converter is supplied,wherein an output terminal of the pre-driver is coupled to an input terminal of the first driver output amplifier and to an input terminal of the second driver output amplifier, while an output terminal of the first driver output amplifier and an output terminal of the second driver output amplifier are allowed to be respectively coupled to one terminal and the other terminal of the series coupling between the motor and the detection resistor,wherein, in the pulse drive operation mode, each of the first driver output amplifier and the second driver output amplifier generates a drive pulse having a pulse width proportional to a voltage level at the output terminal of the pre-driver, andwherein, in a linear drive mode different from the pulse drive operation mode, each of the first driver output amplifier and the second driver output amplifier generates an amplified output signal proportional to the voltage level at the output terminal of the pre-driver. 9. A motor drive control device according to claim 8, wherein, in the pulse drive operation mode, to each of transistors of the first driver output amplifier and the second driver output amplifier, a predetermined bias voltage is supplied to cause each of the first driver output amplifier and the second driver output amplifier to perform a class-D amplifying operation, andwherein, in the linear drive mode, to each of the transistors of the first driver output amplifier and the second driver output amplifier, a bias voltage higher than the predetermined bias voltage is supplied to cause each of the first driver output amplifier and the second driver output amplifier to perform a class-AB amplifying operation. 10. A motor drive control device according to claim 5, wherein the digital control unit includes a digital amplifier formed of a digital multiplier, a third digital multiplier, a fourth digital multiplier, a digital integrator, and a digital adder,wherein the digital amplifier digitally amplifies the digital drive current command value and supplies the amplified digital drive current command value to the digital subtraction circuit,wherein the third digital multiplier performs multiplication between the difference information generated from the digital subtraction circuit and integral gain information to generate and supply a third multiplication result to the digital integrator,wherein the fourth digital multiplier performs multiplication between the difference information generated from the digital subtraction circuit and proportional gain information to generate a fourth multiplication result, andwherein the digital adder performs addition between an output signal from the digital integrator and the fourth multiplication result generated from the fourth digital multiplier to generate and supply digital difference drive current proportion/integration information to an input terminal of the clamp circuit. 11. A motor drive control device according to claim 10, wherein the digital/analog converter is a ΣΔ-type digital/analog converter. 12. A motor drive control device according to claim 11, wherein the analog/digital converter is an over-sampling ΣΔ-type analog/digital converter. 13. A motor drive control device according to claim 12, further comprising: a decimation filter coupled between an output terminal of the over-sampling ΣΔ-type analog/digital converter and each of the digital subtraction circuit of the digital control unit and the first digital multiplier of the counter electromotive voltage detection unit,wherein the decimation filter performs decimation processing for a converted output signal from the over-sampling ΣΔ-type analog/digital converter and lowpass filter processing for suppressing quantization noise in a high-frequency region in the over-sampling ΣΔ-type analog/digital converter. 14. A motor drive control device according to claim 13, further comprising: an offset calibration unit coupled between the output terminal of the over-sampling ΣΔ-type analog/digital converter and each of the digital subtraction circuit of the digital control unit and the first digital multiplier of the counter electromotive voltage detection unit,wherein the offset calibration unit includes a calibration register, and an offset digital subtractor,wherein, in a state where the drive current in the detection resistor is set to substantially zero, error information on an error in the drive current detection amplifier, an error in the analog/digital converter, and an error in the decimation filter is stored in the calibration register, andwherein, in a normal operation, the offset digital subtractor subtracts the error information stored in the calibration register from an output signal from the decimation filter to generate the digital drive current detection signal. 15. A motor drive control device according to claim 14, wherein the motor is a voice coil motor for moving a magnetic head of a hard disk device. 16. A motor drive control device according to claim 15, wherein the digital control unit, the digital/analog converter, the driver output unit, the drive current detection amplifier, the analog/digital converter, the decimation filter, the offset calibration unit, and the counter electromotive voltage detection unit are integrated in a semiconductor chip of a semiconductor integrated circuit. 17. An operation method of a motor drive control device including a digital control unit, a digital/analog converter, a driver output unit, a drive current detection amplifier, an analog/digital converter, and a counter electromotive voltage detection unit, wherein, to an output terminal of the driver output unit, a series coupling between a motor and a detection resistor is allowed to be coupled,wherein the digital control unit generates and supplies a digital drive voltage command signal to an input terminal of the digital/analog converter;wherein the digital/analog converter responds to the digital drive voltage command signal generated from the digital control unit to generate an analog drive voltage command signal,wherein the driver output unit responds to the analog drive voltage command signal generated from the digital/analog converter to generate a drive output signal for driving the series coupling between the motor and the detection resistor,wherein the drive current detection amplifier responds to a drive current flowing in the detection resistor to generate a drive current analog amplified signal,wherein the analog/digital converter responds to the drive current analog amplified signal generated from the drive current detection amplifier to generate a digital drive current detection signal,wherein the counter electromotive voltage detection unit includes a first digital multiplier, a digital subtractor, a second digital multiplier, a first register, and a second register,the first digital multiplier performs multiplication between the digital drive current detection signal generated from the analog/digital converter and first gain information stored in the first register to generate a first multiplication result,wherein the digital subtractor performs subtraction between the digital drive voltage command signal generated from the digital control unit and the first multiplication result generated from the first digital multiplier to generate a subtraction result N,wherein the second digital multiplier performs multiplication between the subtraction result generated from the digital subtractor and second gain information stored in the second register to generate digital counter electromotive voltage information as information on a second multiplication result,wherein the digital drive voltage command signal generated from the digital control unit is set to a predetermined value to generate a condition which maintains a speed of the motor and a counter electromotive voltage at substantially zero, andwherein, under the condition, the first gain information which sets a value of the digital counter electromotive voltage information generated from the second digital multiplier to substantially zero is stored in the first register. 18. An operation method of a motor drive control device according to claim 17, wherein, according to a predetermined search algorithm, the first gain information which sets the value of the digital counter electromotive voltage information to substantially zero is allowed to be stored in the first register. 19. An operation method of a motor drive control device according to claim 18, wherein the predetermined search algorithm is a binary search. 20. An operation method of a motor drive control device according to claim 17, wherein the digital control unit includes a digital subtraction circuit and a clamp circuit,wherein the digital subtraction circuit generates difference information on a difference between a digital drive current command value supplied from the outside and the digital drive current detection signal generated from the analog/digital converter,wherein the clamp circuit responds to the difference information generated from the digital subtraction circuit to generate the digital drive voltage command signal, andwherein, when the digital drive voltage command signal is generated, the clamp circuit respectively clamps an increase and a decrease in the digital drive voltage command signal due to a decrease in a variation in the drive current resulting from a change in the digital drive current command value to a predetermined maximum value and a predetermined minimum value.
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