A method for developing a custom device, the method including: programming a programmable device, where the programmable device includes a layer of monocrystalline first transistors and alignment marks, the first layer of monocrystalline first transistors is overlaid by interconnection layers, the i
A method for developing a custom device, the method including: programming a programmable device, where the programmable device includes a layer of monocrystalline first transistors and alignment marks, the first layer of monocrystalline first transistors is overlaid by interconnection layers, the interconnection layers are overlaid by a second layer of monocrystalline second transistors, where the interconnection layers include copper or aluminum, where the programming includes use of the second transistors, where the programming includes use of N type transistors and P type transistors, and where the programmable device includes at least one programmable connection; and then a step of producing a volume device according to a specific programmed design of the programmable device, where the volume device includes the at least one programmable connection replaced with a lithography defined connection, and where the volume device does not have the second layer.
대표청구항▼
1. A method for developing a custom device, the method comprising: programming a programmable device, wherein said programmable device comprises a layer of monocrystalline first transistors and alignment marks, said first layer of monocrystalline first transistors is overlaid by interconnection laye
1. A method for developing a custom device, the method comprising: programming a programmable device, wherein said programmable device comprises a layer of monocrystalline first transistors and alignment marks, said first layer of monocrystalline first transistors is overlaid by interconnection layers, said interconnection layers are overlaid by a second layer of monocrystalline second transistors,wherein said interconnection layers comprise copper or aluminum,wherein said programming comprises use of said second transistors,wherein said programming comprises use of N type transistors and P type transistors, andwherein said programmable device comprises at least one programmable connection; and thena step of producing a volume device according to a specific programmed design of said programmable device, wherein said volume device comprises said at least one programmable connection replaced with a lithography defined connection, andwherein said volume device does not have said second layer. 2. The method according to claim 1, wherein said interconnection layers of said programmable device comprise at least two interconnection strips having a programmable antifuse connection. 3. The method according to claim 1, wherein formation of said second transistors comprises lithography alignment to said alignment marks, andwherein said alignment has less than 40 nm alignment error. 4. The method according to claim 1, wherein formation of said second transistors comprises a step of defect annealing or dopant activation using optical energy. 5. The method according to claim 1, wherein formation of said programmable device comprises a step of layer transfer. 6. The method according to claim 1, wherein formation of said second transistors comprises at least one processing step wherein said second transistors are overlaying said first transistors. 7. The method according to claim 1, wherein said second transistors are horizontally oriented. 8. A method for developing a custom device, the method comprising: programming a programmable device, wherein said programmable device comprises a layer of monocrystalline first transistors and alignment marks, said first layer of monocrystalline first transistors is overlaid by interconnection layers, said interconnection layers are overlaid by a second layer of monocrystalline second transistors,wherein said interconnection layers comprise copper or aluminum,wherein said programming comprises use of said second transistors,wherein said programming comprises use of N type transistors and P type transistors,wherein formation of said second transistors comprises a step of defect annealing or dopant activation using optical energy, andwherein said programmable device comprises at least one programmable connection; andthena step of producing a volume device according to a specific programmed design of said programmable device, wherein said volume device comprises said at least one programmable connection replaced with a lithography defined connection, andwherein said volume device does not have said second layer. 9. The method according to claim 8, wherein said formation of said second transistors comprises lithography alignment to said alignment marks. 10. The method according to claim 8, wherein said interconnection layers of said programmable device comprise at least two interconnection strips having a programmable antifuse connection. 11. The method according to claim 8, wherein formation of said programmable device comprises a step of layer transfer. 12. The method according to claim 8, wherein said second transistors are horizontally oriented. 13. The method according to claim 8, wherein said formation of said second transistors comprises at least one processing step wherein said second transistors are overlaying said first transistors. 14. A method for developing a custom device, the method comprising: programming a programmable device, wherein said programmable device comprises a layer of monocrystalline first transistors and alignment marks, said first layer of monocrystalline first transistors is overlaid by interconnection layers, said interconnection layers are overlaid by a second layer of monocrystalline second transistors,wherein said interconnection layers comprise copper or aluminum,wherein said programming comprises use of said second transistors,wherein said programming comprises use of N type transistors and P type transistors,wherein formation of said programmable device comprises a step of layer transfer, andwherein said programmable device comprises at least one programmable connection;and thena step of producing a volume device according to a specific programmed design of said programmable device, wherein said volume device comprises said at least one programmable connection replaced with a lithography defined connection, andwherein said volume device does not have said second layer. 15. The method according to claim 14, wherein said interconnection layers of said programmable device comprise at least two interconnection strips having a programmable antifuse connection. 16. The method according to claim 14, wherein formation of said second transistors comprises lithography alignment to said alignment marks. 17. The method according to claim 14, wherein formation of said second transistors comprises a step of defect annealing or dopant activation using optical energy. 18. The method according to claim 14, wherein said second transistors are horizontally oriented. 19. The method according to claim 14, wherein said layer transfer comprises an ion-cut. 20. The method according to claim 14, wherein formation of said second transistors comprises at least one processing step wherein said second transistors are overlaying said first transistors.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (345)
Bernstein, Kerry; Coteus, Paul W.; Emma, Philip G., 3-dimensional integrated circuit architecture, structure and method for fabrication thereof.
Hamm Robert Alan ; Kopf Rose Fasano ; Pinzone Christopher James ; Ryan Robert William ; Tate Alaric, Alignment techniques for epitaxial growth processes.
Silverstein Louis D. (Scottsdale AZ) Bernot Anthony J. (Gilbert AZ), Apparatus and method for an electronically controlled color filter for use in information display applications.
Mule,Tony; Meindl,James D.; Gaylord,Thomas K., Back-side-of-die, through-wafer guided-wave optical clock distribution networks, method of fabrication thereof, and uses thereof.
Kellar, Scot A.; Kim, Sarah E.; List, R. Scott, Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack.
Neville Matthew (Champaign IL) Fluck David J. (Pesotum IL) Hung Cheng-Hung (Champaign IL) Lucarelli Michael A. (Mattoon IL) Scherber Debra L. (Orangevale CA), Chemical mechanical polishing slurry for metal layers.
Batude, Perrine; Clavelier, Laurent; Jaud, Marie-Anne; Thomas, Olivier; Vinet, Maud, Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT.
Cao Wanqing ; Lee Sang-Yun ; Lo Guo-Qiang ; Lee Shih-Ked, Cobalt silicide structure for improving gate oxide integrity and method for fabricating same.
Kang, Pil-kyu; Choi, Gil-heyun; Bae, Dae-lok; Park, Byung-lyul; Lee, Dong-kak, Conductive layer buried-type substrate, method of forming the conductive layer buried-type substrate, and method of fabricating semiconductor device using the conductive layer buried-type substrate.
Marmillion Patricia McGuinness ; Palagonia Anthony Michael ; Pierson Bernadette Ann ; Schmidt Dennis Arthur, Cooling method for silicon on insulator devices.
Abou-Khalil, Michel J.; Gauthier, Jr., Robert J.; Lee, Tom C.; Li, Junjun; Putnam, Christopher S.; Mitra, Souvick, Design structures for high-voltage integrated circuits.
Abadeer, Wagdi W.; Chatty, Kiran V.; Gauthier, Jr., Robert J.; Rankin, Jed H.; Shi, Yun; Tonti, William R., Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures.
Aronowitz Sheldon ; Puchner Helmut ; Kapre Ravindra A. ; Kimball James P., Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of sil.
Fitch Jon T. (Austin TX) Venkatesan Suresh (Austin TX) Witek Keith E. (Austin TX), Integrated circuit having both vertical and horizontal devices and process for making the same.
New,Bernard J.; Conn,Robert O.; Young,Steven P.; Young,Edel M., Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit.
Shimoto,Tadanori; Kikuchi,Katsumi; Matsui,Koji; Baba,Kazuhiro, Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device.
Vyvoda, Michael A.; Herner, S. Brad; Petti, Christopher J.; Walker, Andrew J., Inverted staggered thin film transistor with salicided source/drain structures and method of making same.
Rohatgi Ajeet (Murrysville PA) Rai-Choudhury Prosenjit (Export PA) Gigante Joseph R. (Beltsville MD) Singh Ranbir (State College PA) Fonash Stephen J. (State College PA), Low temperature process for annealing shallow implanted N+/P junctions.
Dawson Robert ; Fulford ; Jr. H. Jim ; Gardner Mark I. ; Hause Frederick N. ; Michael Mark W. ; Moore Bradley T. ; Wristers Derick J., Method and apparatus for in situ anneal during ion implant.
Iriguchi, Chiharu, Method for fabricating semiconductor device, and electro-optical device, integrated circuit and electronic apparatus including the semiconductor device.
Leas James Marc (South Burlington VT) Voldman Steven Howard (South Burlington VT), Method for forming a monolithic electronic module by dicing wafer stacks.
Zavracky Paul M. (Norwood MA) Zavracky Matthew (Attleboro MA) Vu Duy-Phach (Taunton MA) Dingle Brenda (Mansfield MA), Method for forming three dimensional processor using transferred thin film circuits.
Chan Kevin Kok ; D'Emic Christopher Peter ; Jones Erin Catherine ; Solomon Paul Michael ; Tiwari Sandip, Method for making bonded metal back-plane substrates.
Kugimiya Koichi (Toyonaka JPX) Akiyama Shigenobu (Hirakata JPX) Fuse Genshu (Hirakata JPX), Method of fabricating a multi-layer type semiconductor device including crystal growth by spirally directing energy beam.
Harder Christoph S. (Zurich CHX) Jaeckel Heinz (Kilchberg CHX) Wolf Hans P. (Zurich CHX), Method of fabricating a self-aligned metal-semiconductor FET having an insulator spacer.
Norman Michael P. (Chandler AZ) Harvey ; III Thomas B. (Scottsdale AZ) Zhu Xiaodong T. (Chandler AZ), Method of fabricating an integrated multicolor organic led array.
Kwon, Jang yeon; Han, Min koo; Cho, Se young; Park, Kyung bae; Kim, Do young; Lee, Min cheol; Han, Sang myeon; Noguchi, Takashi; Park, Young soo; Jung, Ji sim, Method of fabricating poly-crystalline silicon thin film and method of fabricating transistor using the same.
Robert William McClelland ; Noa More Rensing ; Mark Bradley Spitzer ; Paul Daniel Aquilino ; Paul Martin Zavracky, Method of fabrication of a torsional micro-mechanical mirror system.
Anderson James M. (Huntington Beach CA) Coulson Andrew R. (Santa Monica CA) Demaioribus Vincent J. (Redondo Beach CA) Nicholas Henry T. (Redondo Beach CA), Method of making an adaptive configurable gate array.
Kang Sang-Won (Daejeon KRX) Yu Hyun-Kyu (Daejeon KRX) Kang Won-Gu (Daejeon KRX), Method of manufacturing a semiconductor device having buried elements with electrical characteristic.
Ho, ChiaHua; Lai, Erh Kun; Hsieh, Kuang Yeu, Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states.
Stephen Ross Forrest ; Mark Edward Thompson ; Paul Edward Burrows ; Dennis Matthew McCarty ; Linda Susan Sapochak ; Jon Andrew Cronin, Mixed vapor deposited films for electroluminescent devices.
Forrest Stephen Ross ; Thompson Mark Edward ; Burrows Paul Edward ; Sapochak Linda Susan ; McCarty Dennis Matthew, Multicolor organic light emitting devices.
Forrest Stephen Ross ; Thompson Mark Edward ; Burrows Paul Edward ; Sapochak Linda Susan ; McCarty Dennis Matthew, Multicolor organic light emitting devices.
Forrest Stephen Ross ; Thompson Mark Edward ; Burrows Paul Edward ; Sapochak Linda Susan ; McCarty Dennis Matthew, Multicolor organic light emitting devices.
Jang, Jae Hoon; Jung, Soon Moon; Kim, Jong Hyuk; Rah, Young Seop; Park, Han Byung, Non-volatile memory devices including etching protection layers and methods of forming the same.
Koh, Gwan-Hyeob; Ha, Dae-Won, Non-volatile memory devices including stacked NAND-type resistive memory cell strings and methods of fabricating the same.
Kim, Sarah E.; List, R. Scott; Kellar, Scot A., Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices.
Kim,Sarah E.; List,R. Scott; Kellar,Scot A., Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices.
Breitwisch, Matthew J.; Ditlow, Gary S.; Franceschini, Michele M.; Lastras-Montano, Luis A.; Montoye, Robert K.; Rajendran, Bipin, Resistive memory devices having a not-and (NAND) structure.
Thomas, Olivier; Batude, Perrine; Pouydebasque, Arnaud; Vinet, Maud, SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable.
Nemati Farid ; Plummer James D., Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches.
Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Semiconductor component having plate, stacked dice and conductive vias.
Saito Keishi (Nabari JPX) Fujioka Yasushi (Ueno JPX), Semiconductor device having a semiconductor region in which a band gap being continuously graded.
Mazur Carlos A. (Austin TX) Fitch Jon T. (Austin TX) Hayden James D. (Austin TX) Witek Keith E. (Austin TX), Semiconductor memory device and method of formation.
Zavracky Paul M. (Norwood MA) Fan John C. C. (Chestnut Hill MA) McClelland Robert (Norwell MA) Jacobsen Jeffrey (Hollister CA) Dingle Brenda (Norton MA) Spitzer Mark B. (Sharon MA), Single crystal silicon arrayed devices for display panels.
Iyer Subramanian S. ; Baran Emil ; Mastroianni Mark L. ; Craven Robert A., Single-etch stop process for the manufacture of silicon-on-insulator wafers.
Atkinson Gary M. (1012 - 7th St. ; #15 Santa Monica CA 90403) Courtney M. DuChesne (15127 Blackhawk Mission Hills CA 91345), Split collector vacuum field effect transistor.
Schuehrer,Holger; Hartig,Carsten; Bartsch,Christin; Frohberg,Kai, Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer.
Barbee Steven G. (Dover Plains NY) Leas James M. (Washington DC) Lloyd James R. (Fishkill NY) Nagarajan Arunachala (Wappingers Falls NY), Thin film semiconductor device and method for manufacture.
Chan, Victor; Guarini, Kathryn W.; Ieong, Meikei, Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers.
Alam, Syed M.; Elfadel, Ibrahim M.; Guarini, Kathryn W; Ieong, Meikei; Kudva, Prabhakar N.; Kung, David S.; Lavin, Mark A.; Rahman, Arifur, Three dimensional integrated circuit and method of design.
Takayama,Toru; Maruyama,Junya; Goto,Yuugo; Kuwabara,Hideaki; Yamazaki,Shunpei, Vehicle, display device and manufacturing method for a semiconductor device.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.