Reduction of edge effects from aspect ratio trapping
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/02
H01L-029/04
H01L-021/8252
H01L-021/8258
H01L-027/06
H01L-029/66
H01L-029/267
출원번호
US-0109414
(2013-12-17)
등록번호
US-8994070
(2015-03-31)
발명자
/ 주소
Cheng, Zhiyuan
출원인 / 주소
Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
Slater & Matsil, L.L.P.
인용정보
피인용 횟수 :
0인용 특허 :
256
초록▼
A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduc
A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.
대표청구항▼
1. A structure comprising: a substrate comprising a first crystalline material;a dielectric layer defining at least a first opening and a second opening to the substrate;a first region of a second crystalline material in the first opening and extending above the first opening, the second crystalline
1. A structure comprising: a substrate comprising a first crystalline material;a dielectric layer defining at least a first opening and a second opening to the substrate;a first region of a second crystalline material in the first opening and extending above the first opening, the second crystalline material being lattice mismatched to the first crystalline material, defects arising from the lattice mismatch within the first region terminating at a sidewall of the first opening, the first region having a first lateral edge above the dielectric layer;a second region of the second crystalline material in the second opening and extending above the second opening, defects arising from the lattice mismatch within the second region terminating at a sidewall of the second opening, the second region having a second lateral edge above the dielectric layer;a third material over the dielectric layer and disposed between the first lateral edge and the second lateral edge, the second crystalline material in respective portions of the first region and the second region above the dielectric layer being less defective than the third material; anda device formed in and/or above at least one of the first region and the second region. 2. The structure of claim 1, wherein the third material is a different material from the second crystalline material. 3. The structure of claim 1, wherein the third material is amorphous. 4. The structure of claim 1, wherein the third material is polycrystalline. 5. The structure of claim 1, wherein no device is formed in the third material. 6. The structure of claim 1 further comprising a planar device layer over the second crystalline material and the third material, the device being formed at least partially in the planar device layer. 7. A structure comprising: a substrate comprising a first crystalline material;a dielectric layer over the substrate and having a top surface, the dielectric layer defining at least a first opening from the top surface to the substrate;a first region of a second crystalline material in the first opening, the second crystalline material being lattice mismatched to the first crystalline material, defects arising from the lattice mismatch within the first region terminating at a sidewall of the first opening;a second region of a third crystalline material over the first region, the second region having a first lateral edge extending higher than the top surface of the dielectric layer;a third region of a fourth material over the dielectric layer and disposed adjacent the first lateral edge, the third crystalline material in the second region being less defective than the fourth material; anda device formed in and/or above the second region. 8. The structure of claim 7, wherein the second crystalline material and the third crystalline material are a same crystalline material. 9. The structure of claim 7, wherein the second crystalline material and the third crystalline material are different crystalline materials. 10. The structure of claim 7, wherein the second region of the third crystalline material comprises a strain, the first region of the second crystalline material inducing the strain. 11. The structure of claim 7, wherein the fourth material is amorphous. 12. The structure of claim 7, wherein the fourth material is polycrystalline. 13. The structure of claim 7 further comprising a planar device layer over the second region and the third region, the device being formed at least partially in the planar device layer. 14. The structure of claim 7, wherein the first lateral edge is directly over the top surface of the dielectric layer. 15. The structure of claim 7, wherein the dielectric layer further defines a second opening from the top surface to the substrate, a fourth region of the second crystalline material being in the second opening, defects arising from the lattice mismatch within the fourth region terminating at a sidewall of the second opening, a fifth region of the third crystalline material being over the fourth region, the fifth region having a second lateral edge extending higher than the top surface of the dielectric layer, the third region of the fourth material being disposed adjacent the second lateral edge. 16. A structure comprising: a first dielectric sidewall, a dielectric surface, and a second dielectric sidewall over a substrate comprising a first crystalline material, the dielectric surface extending from an upper edge of the first dielectric sidewall to an upper edge of the second dielectric sidewall;a first region of a second crystalline material over the substrate and extending above the upper edge of the first dielectric sidewall, the second crystalline material being lattice mismatched to the first crystalline material, defects arising from the lattice mismatch within the first region terminating at the first dielectric sidewall, the first region having a first lateral edge above the dielectric surface;a second region of the second crystalline material over the substrate and extending above the upper edge of the second dielectric sidewall, defects arising from the lattice mismatch within the second region terminating at the second dielectric sidewall, the second region having a second lateral edge above the dielectric surface;a third material over the dielectric surface and disposed between the first lateral edge and the second lateral edge, the second crystalline material in respective portions of the first region and the second region above the respective upper edges being less defective than the third material; anda device formed in and/or above at least one of the first region and the second region. 17. The structure of claim 16, wherein the third material is a different material from the second crystalline material. 18. The structure of claim 16, wherein the third material is amorphous. 19. The structure of claim 16, wherein the third material is polycrystalline. 20. The structure of claim 16 further comprising a planar device layer over the second crystalline material and the third material, the device being formed at least partially in the planar device layer.
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Mirabedini,Mohammad R.; Sukharev,Valeriy, Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide.
Bean John C. (New Providence NJ) Higashi Gregg S. (Basking Ridge NJ) Hull Robert (South Orange NJ) Peticolas Justin L. (Wescosville PA), Article comprising a lattice-mismatched semiconductor heterostructure.
Imer,Bilge M.; Speck,James S.; DenBaars,Steven P., Defect reduction of non-polar and semi-polar III-Nitrides with sidewall lateral epitaxial overgrowth (SLEO).
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Vangieson Edward A. (Lawrenceville NJ) York Pamela K. (Trenton NJ) Connolly John C. (Monmouth Junction NJ), Distributed feedback-channeled substrate planar semiconductor laser.
Shih-Yuan Wang ; Changhua Chen ; Yong Chen ; Scott W. Corzine ; R. Scott Kern ; Richard P. Schneider, Jr., Epitaxial material grown laterally within a trench and method for producing same.
Usui Akira,JPX ; Sakai Akira,JPX ; Sunakawa Haruo,JPX ; Mizuta Masashi,JPX ; Matsumoto Yoshishige,JPX, GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor.
Weichold Mark H. (College Station TX) Kinard William B. (Bryan TX) Kirk Wiley P. (College Station TX), Gate adjusted resonant tunnel diode device and method of manufacture.
Naoki Shibata JP; Jun Ito JP; Toshiaki Chiyo JP; Shizuyo Asami JP; Hiroshi Watanabe JP; Shinya Asami JP, Group III nitride compound semiconductor device and method for producing.
Shibata,Naoki; Ito,Jun; Chiyo,Toshiaki; Asami,Shizuyo; Watanabe,Hiroshi; Asami,Shinya, Group III nitride compound semiconductor device and method for producing the same.
Kuramoto, Masaru; Sunakawa, Haruo, Group III-V compound semiconductor crystal structure and method of epitaxial growth of the same as well as semiconductor device including the same.
Iles, Peter A.; Ho, Frank F.; Yeh, Yea-Chuan M., High efficiency, monolithic multijunction solar cells containing lattice-mismatched materials and methods of forming same.
Ohkubo Yoshiyuki,JPX ; Nishizaka Kan,TRX, Information recording medium, method for manufacturing the medium, and apparatus for manufacturing the medium.
Demeester Piet M. (Gent BEX) Ackaert Ann M. (Gent BEX) Van Daele Peter P. (Aalst BEX) Lootens Dirk U. (Deinze BEX), Integration of GaAs on Si substrates.
Morita, Etsuo, METHOD OF MANUFACTURING CRYSTAL OF III-V COMPOUNDS OF THE NITRIDE SYSTEM, CRYSTAL SUBSTRATE OF III-V COMPOUNDS OF THE NITRIDE SYSTEM, CRYSTAL FILM OF III-V COMPOUNDS OF THE NITRIDE SYSTEM, AND METHOD.
Wu Albert T. (San Jose CA) Nozaki Shinji (Tokyo CA JPX) George Thomas (Albany CA) Lee Sandra S. (Los Altos CA) Umeno Masayoshi (Nagoya JPX), Masking technique for depositing gallium arsenide on silicon.
Pham, Daniel T.; Barr, Alexander L.; Mathew, Leo; Nguyen, Bich-Yen; Vandooren, Anne M.; White, Ted R., Method for forming a double-gated semiconductor device.
Bich-Yen Nguyen ; William J. Taylor, Jr. ; Philip J. Tobin ; David L. O'Meara ; Percy V. Gilbert ; Yeong-Jyh T. Lii ; Victor S. Wang, Method for forming a semiconductor device with an opening in a dielectric layer.
Buynoski, Matthew S.; Dakshina-Murthy, Srikanteswara; Tabery, Cyrus E.; Wang, Haihong; Yang, Chih-Yuh; Yu, Bin, Method for forming fins in a FinFET device using sacrificial carbon layer.
Koike, Masayoshi; Nagai, Seiji, Method for manufacturing group III nitride compound semiconductor and a light-emitting device using group III nitride compound semiconductor.
Meister Thomas (Taufkirchen DEX) Stengl Reinhard (Stadtbergen DEX), Method for producing a laterally limited single-crystal region with selective epitaxy and the employment thereof for man.
Fitzgerald ; Jr. Eugene A. (Ithaca NY) Ast Dieter G. (Ithaca NY), Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers.
Fitzgerald ; Jr. Eugene A. (Ithaca NY) Ast Dieter G. (Ithaca NY), Method for reducing or eliminating interface defects in mismatched semiconductor epilayers.
Djomehri, Ihsan J.; Goo, Jung-Suk; Krishnan, Srinath; Maszara, Witold P.; Pan, James N.; Xiang, Qi, Method of growing as a channel region to reduce source/drain junction capacitance.
Van der Wagt Jan Paul ; Wilk Glen D. ; Wallace Robert M., Method of growing crystalline silicon overlayers on thin amorphous silicon oxide layers and forming by method a resonant tunneling diode.
Calviello Joseph A. (Kings Park NY) Hickman Grayce A. (Hicksville NY), Method of making a monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substr.
Mosher Dan M. (Plano TX) Blanton Cornelia H. (Plano TX) Trogolo Joe R. (Plano TX) Latham Larry (Garland TX) Cotton David R. (Plano TX), Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices.
Singh,Jagar; Hou,Yong Tian; Li,Ming Fu, Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration.
Pankove Jacques I. (Princeton NJ) Wu Chung P. (Trenton NJ), Method of making selective crystalline silicon regions containing entrapped hydrogen by laser treatment.
Thomas, III, Stephen; Elliot, Ken; Chow, Dave, Method of manufacture for 80 nanometer diameter resonant tunneling diode with improved peak-to-valley ratio and resonant tunneling diode therefrom.
Yacobi Ben G. (Natick MA) Zemon Stanley (Brookline MA) Jagannath Chirravuri (Needham MA), Method of manufacturing an heteroepitaxial semiconductor structure.
Koh Risho (Tokyo JPX) Ogura Atsushi (Tokyo JPX), Method of producing a semiconductor on insulating substrate, and a method of forming a transistor thereon.
Kevin J. Linthicum ; Thomas Gehrke ; Robert F. Davis, Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts.
Calviello Joseph A. (Kings Park NY) Hickman Grayce A. (Hicksville NY), Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate.
Calviello Joseph A. (Kings Park NY) Hickman Grayce A. (Hicksville NY), Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate.
Macdonald Perry A. (Culver City CA) Larson Lawrence E. (Bethesda MD) Case Michael G. (Thousand Oaks CA) Matloubian Mehran (Encino CA) Chen Mary Y. (Agoura CA) Rensch David B. (Thousand Oaks CA), Monolithic microwave integrated circuit and method.
Paton, Eric N.; Xiang, Qi; Besser, Paul R.; Lin, Ming-Ren; Ngo, Minh V.; Wang, Haihong, Mosfets incorporating nickel germanosilicided gate and methods for their formation.
Gehrke, Thomas; Linthicum, Kevin J.; Davis, Robert F., Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates.
Nishijima,Kazuki; Senda,Masanobu; Chiyo,Toshiaki; Ito,Jun; Shibata,Naoki; Hayashi,Toshimasa, Process for producing group III nitride compound semiconductor.
Nishida Shoji (Nagahama JPX) Yonehara Takao (Atsugi JPX), Process for producing substrate for selective crystal growth, selective crystal growth process and process for producing.
Cavanaugh Marion E. (792 Paul Ave. Palo Alto CA 94306), Quantum field effect device with source extension region formed under a gate and between the source and drain regions.
Fan John C. C. (Chestnut Hill MA) Tsaur Bor-Yeu (Arlington MA) Gale Ronald P. (Bedford MA) Davis Frances M. (Framingham MA), Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth.
Simmons Jerry A. ; Sherwin Marc E. ; Drummond Timothy J. ; Weckwerth Mark V., Resonant tunneling device with two-dimensional quantum well emitter and base layers.
Salerno Jack P. (Waban MA) Lee Jhang W. (Mansfield MA) McCullough Richard E. (Wrentham MA), Selective OMCVD growth of compound semiconductor materials on silicon substrates.
Sasaki Kazuaki,JPX ; Yamamoto Osamu,JPX, Semiconductor light-emitting device capable of having good stability in fundamental mode of oscillation, decreasing curr.
Liu, Chun-Li; Barr, Alexander L.; Grant, John M.; Nguyen, Bich-Yen; Orlowski, Marius K.; Stephens, Tab A.; White, Ted R.; Thomas, Shawn G., Semiconductor structure with different lattice constant materials and method for forming the same.
Berger, Paul R.; Thompson, Phillip E.; Lake, Roger; Hobart, Karl; Rommel, Sean L., Si-based resonant interband tunneling diodes and method of making interband tunneling diodes.
Kapoor Ashok K. (Palo Alto CA) Ciacchella J. Frank (Sunnyvale CA), Sidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layer.
Kong, Hua-Shuang; Edmond, John Adam; Haberern, Kevin Ward; Emerson, David Todd, Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures.
Kong, Hua-Shuang; Edmond, John Adam; Haberern, Kevin Ward; Emerson, David Todd, Single step pendeo-and lateral epitaxial overgrowth of group III-nitride epitaxial layers with group III-nitride buffer layer and resulting structures.
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Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhi Yuan; Fiorenza, James, Solutions for integrated circuit integration of alternative active area materials.
Belyansky, Michael P.; Chidambarrao, Dureseti; Dokumaci, Omer H.; Doris, Bruce B.; Gluschenkov, Oleg, Structure and method to improve channel mobility by gate electrode stress modification.
Ek Bruce A. (Pelham Manor NY) Iyer Subramanian S. (Yorktown Heights NY) Pitner Philip M. (Wappingers Falls NY) Powell Adrian R. (New Milford CT) Tejwani Manu J. (Yorktown Heights NY), Substrate for tensilely strained semiconductor.
Freundlich Alexandre (Houston TX) Vilela Mauro F. (Houston TX) Bensaoula Abdelhak (Houston TX) Ignatiev Alex (Houston TX), Tandem solar cell with improved tunnel junction.
Bedell,Stephen W.; Domenicucci,Anthony G.; Fogel,Keith E.; Leobandung,Effendi; Sadana,Devendra K., Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer.
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