An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. T
An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
대표청구항▼
1. An integrated circuit comprising: one or more logic blocks configured to generate one or more system operation signals at one or more system operation clock rates;a service processor unit configured to perform one or more debug operations on one or more of the logic blocks, the service processor
1. An integrated circuit comprising: one or more logic blocks configured to generate one or more system operation signals at one or more system operation clock rates;a service processor unit configured to perform one or more debug operations on one or more of the logic blocks, the service processor unit comprising: a control unit configured to control the service processor unit;a memory;an analysis engine; anda bus interface; anda multiplicity of probe lines configured to capture and propagate one or more of the one or more system operation signals from the logic blocks to the service processor unit. 2. The integrated circuit of claim 1, wherein the analysis engine is configured to align signals received from the probe lines. 3. The integrated circuit of claim 1, wherein the analysis engine includes a variable first-in, first-out (FIFO) element. 4. The integrated circuit of claim 1, wherein the analysis engine is configured to store aligned signals in buffer memory. 5. The integrated circuit of claim 1, wherein the service processor unit further comprises a parallel I/O port, wherein data and instructions are sent through the parallel I/O port to the service processor unit from an external console, and wherein result data is provided through the parallel I/O port to the external console. 6. The integrated circuit of claim 1, wherein the service processor unit further comprises a serial I/O port, wherein data and instructions are sent through the serial I/O port to the service processor unit from an external console, and wherein result data is provided through the serial I/O port to the external console. 7. The integrated circuit of claim 1, wherein the service processor unit further comprises a JTAG port, wherein data and instructions are sent through the JTAG port to the service processor unit from an external console, and wherein result data is provided through the JTAG port to the external console. 8. The integrated circuit of claim 1, wherein the multiplicity of probe lines includes at least one analog probe line. 9. The integrated circuit of claim 1, wherein the multiplicity of probe lines includes at least one digital probe line. 10. The integrated circuit of claim 9, wherein the digital probe line comprises at least one storage element and is configured to move one or more of the system operation signals from one or more of the logic blocks to the service processor unit via the bus interface. 11. The integrated circuit of claim 10, wherein the at least one storage element is configured to use a system clock to move the one or more of the system operation signals. 12. The integrated circuit of claim 1, wherein the control unit is configured to execute instructions for providing test signals to one or more of the logic blocks and for retrieving one or more test signal results from one or more of the logic blocks. 13. The integrated circuit of claim 1, wherein the bus interface is a test bus interface. 14. The integrated circuit of claim 1, further comprising: a test access port controller. 15. An integrated circuit comprising: a multiplicity of logic blocks configured to generate one or more system operation signals;a logic analyzer coupled to at least one external interface; anda multiplicity of probe lines configured to propagate signals to the logic analyzer, wherein at least one of the probe lines is configured to propagate at least one of the system operation signals, and wherein the logic analyzer is configured to: store a selected set of the system operation signals for retrieval through the at least one external interface; andalign the selected set of system operation signals. 16. The integrated circuit of claim 15, wherein the logic analyzer includes a variable first-in, first-out (FIFO) element. 17. The integrated circuit of claim 15, wherein at least one of the probe lines is configured to propagate at least one signal representing at least one analog event. 18. The integrated circuit of claim 17, wherein the at least one analog event comprises a ground bounce event. 19. The integrated circuit of claim 15, further comprising an analog-event detection circuit, wherein at least one of the probe lines is configured to propagate one or more signals from the analog-event detection circuit. 20. The integrated circuit of claim 19, wherein the analog-event detection circuit is configured to detect a voltage level. 21. The integrated circuit of claim 15, wherein the multiplicity of probe lines includes at least one digital probe line. 22. An integrated circuit comprising: one or more logic blocks configured to generate one or more system operation signals at one or more system operation clock rates;a service processor unit configured to perform one or more debug operations on one or more of the logic blocks, the service processor unit comprising: a control unit;a memory;an analysis engine; anda bus interface; anda multiplicity of probe lines configured to capture one or more of the one or more system operation signals from the logic blocks to the service processor unit, wherein the analysis engine is configured to align signals received from the probe lines.
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이 특허에 인용된 특허 (91)
Dagostino Thomas P. (Beaverton OR) Frisch Arnold M. (Portland OR), Analog multi-channel probe system.
Yip Aaron S. (Milpitas CA) Lacey Timothy M. (Cupertino CA) Nayak Anup K. (San Jose CA) Nema Rajiv (Sunnyvale CA) Nguyen Han-Kim (Newark CA), Architecture for FPGAs.
Aldereguia Alfredo (Boca Raton FL) Amini Nader (Boca Raton FL) Horne Richard L. (Boynton Beach FL) Lohman Terence J. (Boca Raton FL) Tran Cang N. (Boca Raton FL), Bus interface logic for computer system having dual bus architecture.
De Angelis Douglas J. (Woburn MA) Maddox Henry W. J. (Franklin MA) Peters Arthur (Sudbury MA) Rathbun Donald J. (Methuen MA) Saltmarsh William L. (Brockton MA), Bus monitor with means for selectively capturing trigger conditions.
Ranson Gregory L. ; Bockhaus John W. ; Lesartre Gregg B. ; Knebel Patrick ; Perez Paul L., Circuitry for providing external access to signals that are internal to an integrated circuit chip package.
Crouch Alfred L. (Austin TX) Pressly Matthew D. (Austin TX) Gay James G. (Pflugerville TX) Shepard Clark G. (Austin TX) Laakso Pamela S. (Austin TX), Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data.
Groves Stanley E. (1505 Lime Rock Dr. Round Rock TX 78681) Goler Vernon B. (6808 La Concha Pass Austin TX 78749) Miller Gary L. (8214 Mauai Dr. Austin TX 78749) Nemirovsky Mario (460 Whitman Dr. ; #7, Dedicated service processor with inter-channel communication features.
La Joie Leslie T. (4203 Dauphine Dr. Austin TX 78727) Miller Eugene M. (13112 Marble Falls Cove Austin TX 78729) Dobbs Carl S. (1101 S. Capital of Texas Hwy. ; Bldg. J. Suite 220 Austin TX 78746) Sol, Diagnostic system for run-time monitoring of computer operations.
Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y; Mathieu, Gaetan L., ELECTRICAL CONTACT STRUCTURES FORMED BY CONFIGURING A FLEXIBLE WIRE TO HAVE A SPRINGABLE SHAPE AND OVERCOATING THE WIRE WITH AT LEAST ONE LAYER OF A RESILIENT CONDUCTIVE MATERIAL, METHODS OF MOUNTING.
Swoboda Gary L. (Sugar Land TX) Daniels Martin D. (Houston TX) Coomes Joseph A. (Missouri City TX), Emulation devices, systems and methods utilizing state machines.
Katircioglu Haluk (Irvine CA) De Beule John A. (Rancho Santa Margarita CA) Mukherjee Debaditya (El Toro CA) Whitlock Gary C. (Mission Viejo CA), Error log system for self-testing in very large scale integrated circuit (VLSI) units.
Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
Dosch Daniel G. (793 Evergreen Rd. Severn MD 21144) Bundy Otis A. (6158 Osage Ct. Sykesville MD 21784) Whyms ; III Robert (4754 Ilkley Moor Ln. Ellicott City MD 21043), Improved method for accessing machine state information.
Saadeh Said S. (Plano TX) Farrand Scott C. (Tomball TX) Hernandez Thomas J. (Houston TX) Fulton Paul R. (Plano TX) Mangold Richard P. (Tomball TX) Stupek Richard A. (Houston TX) Barron James E. (Spri, Innate bus monitoring system for computer system manager.
Gheewala Tushar R. (Cupertino CA) Sucar Hector R. (Fremont CA), Interface between IC operational circuitry for coupling test signal from internal test matrix.
Taylor Mark A. (Columbia SC) Harrison Chris A. (Lexington SC) Simpson David L. (West Columbia SC) James Larry C. (West Columbia SC), Intermodule test across system bus utilizing serial test bus.
Levin Arthur L. (Pleasant Valley NY) Rain Don W. (Poughkeepsie NY) Thomas David J. (Poughkeepsie NY), Internal performance monitoring by event sampling.
Gronlund Robert D. ; Willette Brian A. ; Zevin William M., Method and apparatus for correlating logic analyzer state capture data with associated application data structures.
Harold L. McFarland ; David R. Stiles ; Korbin S. Van Dyke ; Shrenik Mehta ; John Gregory Favor ; Dale R. Greenley ; Robert A. Cargnoni, Method and apparatus for debugging an integrated circuit.
Broseghini James L. ; Langan John A. ; Poterek Thomas J., Method and apparatus for scan testing with extended test vector storage in a multi-purpose memory system.
Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system.
Gover, Frank Carl; Levine, Frank Eliot; Olszewski, Bret R.; Roth, Charles Philip; Welbon, Edward Hugh; Wright, Charles, Method and system for selecting and distinguishing an event sequence using an effective address in a processing system.
Jacobs Scott L. (Apex NC) McMahon ; Jr. Maurice T. (Poughkeepsie NY) Nihal Perwaiz (Hopewell Junction NY) Ozmat Burhan (Dallas TX) Schnurmann Henri D. (Monsey NY) Zingher Arthur R. (White Plains NY), Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure.
Klapproth Peter (Eindhoven NLX) Zandveld Frederik (Eindhoven NLX) Bakker Jacobus M. (Eindhoven NLX) Van Loo Gerardus C. (Eindhoven NLX), Microcontroller provided with hardware for supporting debugging as based on boundary scan standard-type extensions.
Dreyer Robert S. (Sunnyvale CA) Alpert Donald B. (Santa Clara CA) Modi Nimish H. (San Jose CA) Tripp Mike J. (Forest Grove OR), Microprocessor with an external command mode for diagnosis and debugging.
Jacobs Scott L. (Peekskill NY) Nihal Perwaiz (Hopewell Junction NY) Ozmat Burhan (Peekskill NY) Schnurmann Henri D. (Monsey NY) Zingher Arthur R. (White Plains NY), Module for packaging semiconductor integrated circuit chips on a base substrate.
Gibson Walter E. ; Sprouse Jeffery A. ; Lipiansky Eduardo M. ; Khakbaz Javad ; Plum Michael A. ; Manela Philip R. ; Yamamoto Ko, Real time observation serial scan test architecture.
Tanizaki, Tetsushi; Hamamoto, Takeshi, Semiconductor memory device allowing mounting of built-in self test circuit without addition of interface specification.
Ranson Gregory L. ; Bockhaus John W. ; Lesartre Gregg B. ; Brockmann Russell C. ; Naas Robert E. ; Lotz Jonathan P. ; Hunt Douglas B. ; Knebel Patrick ; Perez Paul L. ; Mangelsdorf Steven T., System and method for on-chip debug support and performance monitoring in a microprocessor.
Tobin Paul G. ; Naaseh-Shahry Hosein, Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger a.
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