Semiconductor device with advanced pad structure resistant to plasma damage and method for forming the same
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/78
H01L-021/768
H01L-023/00
H01L-023/522
출원번호
US-0792744
(2013-03-11)
등록번호
US-9006900
(2015-04-14)
발명자
/ 주소
Wang, Hung-Chih
Liang, Yao-Hsiang
출원인 / 주소
Taiwan Semiconductor Manufacturing Co., Ltd.
대리인 / 주소
Duane Morris LLP
인용정보
피인용 횟수 :
2인용 특허 :
3
초록▼
A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer
A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.
대표청구항▼
1. A semiconductor device comprising: a semiconductor device having at least one metal layer including a top metal layer;a dielectric material disposed over said top metal layer;a dense material layer disposed over said dielectric material, said dense material layer comprising a high-density, low-ro
1. A semiconductor device comprising: a semiconductor device having at least one metal layer including a top metal layer;a dielectric material disposed over said top metal layer;a dense material layer disposed over said dielectric material, said dense material layer comprising a high-density, low-roughness barrier-type material;a barrier layer disposed over said dense material layer; andan aluminum-containing connective pad disposed over said barrier layer,said dense material layer and said barrier layer formed of the same material and said dense material layer having a greater density than said barrier layer. 2. The semiconductor device as in claim 1, wherein said barrier layer is disposed directly on said dense material layer. 3. The semiconductor device as in claim 1, wherein said at least one metal layer comprises 5-10 metal layers and said semiconductor device includes a plurality of metal gate MOS transistors. 4. The semiconductor device as in claim 3, wherein said dense material layer includes a density of about 18-22 g/cm3. 5. The semiconductor device as in claim 4, wherein said dense material layer includes a surface roughness less than a surface roughness of said barrier layer. 6. The semiconductor device as in claim 4, wherein said dense material layer includes a thickness of about 25-100 angstroms, said barrier layer includes a thickness in a range of about 500-700 angstroms and said aluminum-containing connective pad is coupled to said top metal layer through an opening that extends at least through said dielectric material. 7. The semiconductor device as in claim 1, wherein said dense material layer and said barrier layer are each formed of a first material, and said first material comprises one of Ta, TaN, Ti, and TiN. 8. The semiconductor device as in claim 1, wherein said dense material layer includes a surface roughness less than about 5 nm. 9. The semiconductor device as in claim 8, wherein said barrier layer includes a surface roughness greater than said surface roughness of said dense material layer and within a range of about 8-15 nm. 10. The semiconductor device as in claim 1, further comprising said aluminum-containing connective pad coupled to said top metal layer through an opening that extends at least through said dielectric material and further contacting a solder bump and wherein each of said dense material layer and said barrier layer is formed of TaN and said aluminum-containing connective pad has a thickness in a range of about 20K-40K angstroms. 11. A semiconductor device comprising: a semiconductor device having at least one metal layer including a top metal layer;a dielectric material disposed over said top metal layer;a dense material layer disposed over said dielectric material, said dense material layer comprising a high-density, low-roughness barrier-type material;a barrier layer disposed over said dense material layer and formed of the same material as said dense material layer; andan aluminum-containing connective pad disposed over said barrier layer,wherein said dense material layer includes a density greater than a density of said barrier layer. 12. The semiconductor device as in claim 11, wherein said barrier layer is disposed directly on said dense material layer. 13. The semiconductor device as in claim 11, wherein said dense material layer includes a surface roughness less than a surface roughness of said barrier layer. 14. The semiconductor device as in claim 11, wherein said aluminum-containing connective pad is coupled to said top metal layer through an opening that extends at least through said dielectric material. 15. The semiconductor device as in claim 11, wherein said dense material and said barrier layer are each formed of one of Ta, TaN, Ti, and TiN and said dense material layer includes a surface roughness less than about 5 nm. 16. A semiconductor device comprising: a semiconductor device having a plurality of metal layers including a top metal layer;an antenna structure formed of two of said metal layers disposed beneath said top metal layer in a first device region;a dielectric material disposed over said top metal layer;a dense material layer disposed over said dielectric material in a second device region, said dense material layer comprising a high-density, low-roughness barrier-type material;a barrier layer disposed over said dense material layer and formed of the same material as said dense material layer; andan aluminum-containing connective pad disposed over said barrier layer,wherein said dense material layer includes a surface roughness less than a surface roughness of said barrier layer and a greater density than said barrier layer. 17. The semiconductor device as in claim 16, wherein said barrier layer is disposed directly on said dense material layer. 18. The semiconductor device as in claim 16, wherein said dense material and said barrier layer are each formed of one of Ta, TaN, Ti, In, Ga and TiN and said dense material layer includes a surface roughness less than about 5 nm. 19. The semiconductor device as in claim 16, claim 1, wherein said dense material layer includes a surface roughness less than about 5 nm and said barrier layer includes a surface roughness within a range of about 8-15 nm. 20. The semiconductor device as in claim 16, further comprising said aluminum-containing connective pad coupled to said top metal layer through an opening that extends at least through said dielectric material and further contacting a solder bump and wherein each of said dense material layer and said barrier layer is formed of TaN and said aluminum-containing connective pad has a thickness in a range of about 20K-40K angstroms.
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이 특허에 인용된 특허 (3)
Lin, Mou-Shiung; Lee, Jin-Yuan; Lo, Hsin-Jung; Yang, Ping-Jung; Liu, Te-Sheng, Integrated circuit chip using top post-passivation technology and bottom structure technology.
Burrell, Lloyd G.; Wong, Kwong H.; Kelly, Adreanne A.; McKnight, Samuel R., Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad.
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