최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
---|---|
국제특허분류(IPC7판) |
|
출원번호 | US-0740191 (2013-01-12) |
등록번호 | US-9009641 (2015-04-14) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 13 인용 특허 : 520 |
A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source an
A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.
1. A semiconductor device, comprising: a substrate;a first transistor having a source region and a drain region within a first diffusion fin, the first diffusion fin structured to project from a surface of the substrate, the first diffusion fin structured to extend lengthwise in a first direction fr
1. A semiconductor device, comprising: a substrate;a first transistor having a source region and a drain region within a first diffusion fin, the first diffusion fin structured to project from a surface of the substrate, the first diffusion fin structured to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin;a second transistor having a source region and a drain region within a second diffusion fin, the second diffusion fin structured to project from the surface of the substrate, the second diffusion fin structured to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, the second diffusion fin positioned next to and spaced apart from the first diffusion fin,wherein either the first end or the second end of the second diffusion fin is positioned in the first direction at a location between the first end and the second end of the first diffusion fin, the location offset in the first direction from the first end and the second end of the first diffusion fin. 2. A semiconductor device as recited in claim 1, wherein the first and second transistors are located at different positions in the second direction perpendicular to the first direction. 3. A semiconductor device as recited in claim 1, wherein each of the first and second transistors is a three-dimensionally gated transistor. 4. A semiconductor device as recited in claim 1, wherein the first transistor includes a first linear-shaped gate electrode structure that extends lengthwise in a second direction perpendicular to the first direction as viewed from above the substrate, and wherein the second transistor includes a second linear-shaped gate electrode structure that extends lengthwise in the second direction perpendicular to the first direction as viewed from above the substrate,wherein at least one of the first and second ends of the first diffusion fin is positioned in the first direction between the first and second linear-shaped gate electrode structures, andwherein at least one of the first and second ends of the second diffusion fin is positioned in the first direction between the first and second linear-shaped gate electrode structures. 5. A semiconductor device as recited in claim 4, wherein the first linear-shaped gate electrode structure is positioned next to and spaced apart from the second linear-shaped gate electrode structure. 6. A semiconductor device as recited in claim 4, further comprising: a linear-shaped local interconnect structure that extends in the second direction and that is positioned between the first and second linear-shaped gate electrode structures. 7. A semiconductor device as recited in claim 6, wherein the linear-shaped local interconnect structure is substantially centered in the first direction between the first and second linear-shaped gate electrode structures. 8. A semiconductor device as recited in claim 6, wherein the linear-shaped local interconnect structure connects to one or more of the first and second diffusion fins. 9. A semiconductor device as recited in claim 4, further comprising: a linear-shaped local interconnect structure that extends in the first direction and that is positioned between the first and second diffusion fins. 10. A semiconductor device as recited in claim 9, wherein the linear-shaped local interconnect structure is substantially centered in the second direction between the first and second diffusion fins. 11. A semiconductor device as recited in claim 9, wherein the linear-shaped local interconnect structure connects to one or more of the first and second gate electrode structures. 12. A semiconductor device as recited in claim 9, wherein the linear-shaped local interconnect structure is a first linear-shaped local interconnect structure, the semiconductor device further including a second linear-shaped local interconnect structure that extends in the second direction and that is positioned between the first and second linear-shaped gate electrode structures. 13. A semiconductor device as recited in claim 12, wherein the second linear-shaped local interconnect structure is substantially centered in the first direction between the first and second linear-shaped gate electrode structures. 14. A semiconductor device as recited in claim 12, wherein the second linear-shaped local interconnect structure connects to one or more of the first diffusion fin, the second diffusion fin. 15. A semiconductor device as recited in claim 12, wherein the first linear-shaped local interconnect structure is a first linear segment of a two-dimensionally varying non-linear local interconnect structure, and wherein the second linear-shaped local interconnect structure is a second linear segment of the two-dimensionally varying non-linear local interconnect structure. 16. A semiconductor device as recited in claim 15, wherein the first and second linear-shaped local interconnect structures are connected to each other. 17. A semiconductor device as recited in claim 4, further comprising: a contact structure positioned between the first and second diffusion fins. 18. A semiconductor device as recited in claim 17, wherein the contact structure is substantially centered between the first and second diffusion fins. 19. A semiconductor device as recited in claim 18, wherein the contact structure connects to either the first gate electrode structure or the second gate electrode structure. 20. A semiconductor device as recited in claim 4, further comprising: a contact structure positioned between the first and second gate electrode structures. 21. A semiconductor device as recited in claim 20, wherein the contact structure is substantially centered between the first and second gate electrode structures. 22. A semiconductor device as recited in claim 20, further comprising: a conductive interconnect structure positioned in the second direction between first and second diffusion fins, wherein the contact structure connects to the conductive interconnect structure. 23. A semiconductor device as recited in claim 22, wherein the conductive interconnect structure is a lowest level interconnect structure extending in the first direction that is not a diffusion fin. 24. A semiconductor device as recited in claim 22, wherein the conductive interconnect structure is higher-level interconnect structure. 25. A semiconductor device as recited in claim 20, further comprising: a conductive interconnect structure positioned in the first direction between first and second diffusion fins, wherein the contact structure connects to a conductive interconnect structure. 26. A semiconductor device as recited in claim 4, further comprising: one or more interconnect structures, wherein some of the one or more interconnect structures include one or more interconnect segments that extend in the first direction. 27. A semiconductor device as recited in claim 26, wherein some of the one or more interconnect segments that extend in the first direction are positioned between the first and second diffusion fins. 28. A semiconductor device as recited in claim 26, wherein some of the one or more interconnect segments that extend in the first direction are positioned over either the first diffusion fin or the second diffusion fin. 29. A semiconductor device as recited in claim 26, wherein the one or more interconnect segments that extend in the first direction are positioned in accordance with a second direction interconnect pitch as measured in the second direction between respective first direction oriented centerlines of the one or more interconnect segments. 30. A semiconductor device as recited in claim 29, wherein the first and second diffusion fins are positioned in accordance with a diffusion fin pitch as measured in the second direction between respective first direction oriented centerlines of the first and second diffusion fins, and wherein the second direction interconnect pitch is a rational multiple of the diffusion fin pitch, the rational multiple defined as a ratio of integer values. 31. A semiconductor device as recited in claim 29, wherein each of the first and second diffusion fins is centerline positioned in accordance with either a first diffusion fin pitch as measured in the second direction or a second diffusion fin pitch as measured in the second direction, wherein the first and second diffusion pitches successively alternate in the second direction, and wherein an average diffusion fin pitch is an average of the first and second diffusion fin pitches, and wherein the second direction interconnect pitch is a rational multiple of the average diffusion fin pitch, the rational multiple defined as a ratio of integer values. 32. A semiconductor device as recited in claim 31, wherein the first diffusion fin pitch is equal to the second diffusion fin pitch. 33. A semiconductor device as recited in claim 31, wherein the first diffusion fin pitch is different than the second diffusion fin pitch. 34. A semiconductor device as recited in claim 26, wherein the one or more interconnect structures include either a local interconnect structure, a higher-level interconnect structure formed at a level above a local interconnect structure relative to the substrate, or both a local interconnect structure and a higher-level interconnect structure formed at a level above the local interconnect structure relative to the substrate, wherein the local interconnect structure is a lowest level interconnect structure that is not a diffusion fin. 35. A semiconductor device as recited in claim 26, wherein each of the first and second diffusion fins is centerline positioned in accordance with either a first diffusion fin pitch as measured in the second direction or a second diffusion fin pitch as measured in the second direction, wherein the first and second diffusion pitches successively alternate in the second direction, and wherein an average diffusion fin pitch is an average of the first and second diffusion fin pitches, and wherein the one or more interconnect segments that extend in the first direction are centerline positioned in accordance with either a first interconnect pitch as measured in the second direction or a second interconnect pitch as measured in the second direction, wherein the first and second interconnect pitches successively alternate in the second direction, and wherein an average interconnect pitch is an average of the first and second interconnect pitches,wherein the average interconnect pitch is a rational multiple of the average diffusion fin pitch, the rational multiple defined as a ratio of integer values. 36. A semiconductor device as recited in claim 35, wherein the first diffusion fin pitch is equal to the second diffusion fin pitch, and the first interconnect pitch is equal to the second interconnect pitch. 37. A semiconductor device as recited in claim 35, wherein the first diffusion fin pitch is different than the second diffusion fin pitch, and the first interconnect pitch is different than the second interconnect pitch. 38. A semiconductor device as recited in claim 35, wherein the first diffusion fin pitch is equal to the first interconnect pitch, and the second diffusion fin pitch is equal to the second interconnect pitch. 39. A semiconductor device as recited in claim 4, further comprising: one or more interconnect structures, wherein some of the one or more interconnect structures include one or more interconnect segments that extend in the second direction. 40. A semiconductor device as recited in claim 39, wherein some of the one or more interconnect segments that extend in the second direction are positioned between the first and second gate electrode structures. 41. A semiconductor device as recited in claim 39, wherein some of the one or more interconnect segments that extend in the second direction are positioned over either the first gate electrode structure or the second gate electrode structure. 42. A semiconductor device as recited in claim 39, wherein the one or more interconnect segments that extend in the second direction are positioned in accordance with a first direction interconnect pitch as measured in the first direction between respective second direction oriented centerlines of the one or more interconnect segments. 43. A semiconductor device as recited in claim 42, wherein the first and second gate electrode structures are positioned in accordance with a gate electrode pitch as measured in the first direction between respective second direction oriented centerlines of the first and second gate electrode structures, and wherein the first direction interconnect pitch is a rational multiple of the gate electrode pitch, the rational multiple defined as a ratio of integer values. 44. A semiconductor device as recited in claim 39, wherein the one or more interconnect structures include either a local interconnect structure, a higher-level interconnect structure, or a combination thereof, wherein the local interconnect structure is a lowest level interconnect structure that is not a diffusion fin, and wherein the higher-level interconnect structure is an interconnect structure formed at a level above the local interconnect structure relative to the substrate. 45. A semiconductor device as recited in claim 1, further comprising: a first plurality of transistors each having a respective source region and a respective drain region formed by a respective diffusion fin, each diffusion fin of the first plurality of transistors structured to project from the surface of the substrate, each diffusion fin of the first plurality of transistors structured to extend lengthwise in the first direction from a first end to a second end of the respective diffusion fin, wherein the first ends of the diffusion fins of the first plurality of transistors are substantially aligned with each other in the first direction,a second plurality of transistors each having a respective source region and a respective drain region formed by a respective diffusion fin, each diffusion fin of the second plurality of transistors structured to project from the surface of the substrate, each diffusion fin of the second plurality of transistors structured to extend lengthwise in the first direction from a first end to a second end of the respective diffusion fin, wherein the first ends of the diffusion fins of the second plurality of transistors are substantially aligned with each other in the first direction, andwherein one or more of the first ends of the diffusion fins of the second plurality of transistors are positioned in the first direction between the first and second ends of one or more of the diffusion fins of the first plurality of transistors. 46. A semiconductor device as recited in claim 45, wherein each of the first ends of the diffusion fins of the second plurality of transistors is positioned in the first direction between the first and second ends of one or more of the diffusion fins of the first plurality of transistors. 47. A semiconductor device as recited in claim 46, wherein at least one of the diffusion fins of the second plurality of transistors is positioned next to and spaced apart from at least one diffusion fin of the first plurality of transistors. 48. A semiconductor device as recited in claim 45, wherein the first plurality of transistors includes either n-type transistors, p-type transistors, or a combination of n-type and p-type transistors, and wherein the second plurality of transistors includes either n-type transistors, p-type transistors, or a combination of n-type and p-type transistors. 49. A semiconductor device as recited in claim 45, wherein the first plurality of transistors are n-type transistors and the second plurality of transistors are p-type transistors. 50. A semiconductor device as recited in claim 45, wherein the first and second pluralities of diffusion fins are positioned to have their respective first direction oriented centerlines substantially aligned to a diffusion fin alignment grating defined by a first diffusion fin pitch as measured in the second direction perpendicular to the first direction and a second diffusion fin pitch as measured in the second direction, where the first and second diffusion fin pitches occur in an alternating sequence in the second direction. 51. A semiconductor device as recited in claim 50, wherein the diffusion fins of the first and second pluralities of transistors collectively occupy portions at least eight consecutive alignment positions of the diffusion fin alignment grating. 52. A method of fabricating a semiconductor device, comprising: providing a substrate;forming a first transistor on the substrate, the first transistor having a source region and a drain region within a first diffusion fin, the first diffusion fin formed to project from a surface of the substrate, the first diffusion fin formed to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin;forming a second transistor on the substrate, the second transistor having a source region and a drain region within a second diffusion fin, the second diffusion fin formed to project from the surface of the substrate, the second diffusion fin formed to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, the second diffusion fin formed at a position next to and spaced apart from the first diffusion fin,wherein either the first end or the second end of the second diffusion fin is formed at a location in the first direction between the first end and the second end of the first diffusion fin, the location offset in the first direction from the first end and the second end of the first diffusion fin.
Copyright KISTI. All Rights Reserved.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.