$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Semiconductor memory device and method of fabricating the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/20
  • H01L-049/02
  • H01L-027/105
  • H01L-027/108
  • H01L-027/115
  • H01L-021/84
  • H01L-027/06
  • H01L-027/12
출원번호 US-0175652 (2011-07-01)
등록번호 US-9012292 (2015-04-21)
우선권정보 KR-10-2009-0063938 (2010-07-02)
발명자 / 주소
  • Lee, Sang-Yun
출원인 / 주소
  • Lee, Sang-Yun
대리인 / 주소
    Martinez, Greg L
인용정보 피인용 횟수 : 0  인용 특허 : 73

초록

A method for fabricating semiconductor memory device, includes providing a semiconductor substrate; forming a lower region which includes a first data storage device, which is carried by the semiconductor substrate; forming a switching device which is carried by the first data storage device; and fo

대표청구항

1. A method for fabricating semiconductor memory device, comprising: providing a semiconductor substrate;forming a lower region, which includes a first data storage device, wherein the lower region is carried by the semiconductor substrate;forming a switching device, which is carried by the first da

이 특허에 인용된 특허 (73)

  1. Kub Francis J. ; Temple Victor ; Hobart Karl ; Neilson John, Advanced methods for making semiconductor devices by low temperature direct bonding.
  2. Kellar, Scot A.; Kim, Sarah E.; List, R. Scott, Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack.
  3. Lee, Sang-Yun, Bonded semiconductor structure and method of fabricating the same.
  4. Raby Joseph S. (W. Melbourne FL), Bonding technique to join two or more silicon wafers.
  5. Lee, Sang Yun, Electronic circuit with embedded memory.
  6. Aronowitz Sheldon ; Puchner Helmut ; Kapre Ravindra A. ; Kimball James P., Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of sil.
  7. Fitch Jon T. (Austin TX) Venkatesan Suresh (Austin TX) Witek Keith E. (Austin TX), Integrated circuit having both vertical and horizontal devices and process for making the same.
  8. Tiwari, Sandip, Low temperature semiconductor layering and three-dimensional electronic circuits using the layering.
  9. Geusic, Joseph E., Low temperature silicon wafer bond process with bulk material bond strength.
  10. Kennedy James R. (Huntington NY) Ting Edmund Y. (Oyster Bay NY), Method for diffusion bonding of alloys having low solubility oxides.
  11. Pramanick Shekhar (Fremont CA) Nayak Deepak (Santa Clara CA), Method for electrically conductive metal-to-metal bonding.
  12. Kub Francis J. ; Hobart Karl D., Method for fabricating singe crystal materials over CMOS devices.
  13. Lee,Sang Yun, Method for making a three-dimensional integrated circuit structure.
  14. Chan Kevin Kok ; D'Emic Christopher Peter ; Jones Erin Catherine ; Solomon Paul Michael ; Tiwari Sandip, Method for making bonded metal back-plane substrates.
  15. Ito Tatsuo (Joetsu JPX) Uchiyama Atsuo (Chiisagata JPX) Fukami Masao (Nagano JPX), Method for preparing a substrate for semiconductor devices.
  16. Ichikawa Takeshi (Zama JPX) Yonehara Takao (Atsugi JPX) Sakaguchi Kiyofumi (Atsugi JPX), Method for preparing semiconductor member.
  17. Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Method for producing semiconductor substrate.
  18. Brian S. Doyle, Method of delaminating a thin film using non-thermal techniques.
  19. Ramm Peter (Pfaffenhofen DEX) Buchner Reinhold (Unterfohring DEX), Method of making a three-dimensional integrated circuit.
  20. Shunpei Yamazaki JP, Method of manufacturing a semiconductor device.
  21. Aspar Bernard,FRX ; Biasse Beatrice,FRX ; Bruel Michel,FRX, Method of obtaining a thin film of semiconductor material.
  22. Ulyashin, Alexander; Usenko, Alexander, Method of producing a thin layer of crystalline material.
  23. Aspar, Bernard; Bruel, Michel; Poumeyrol, Thierry, Method of producing a thin layer of semiconductor material.
  24. Aspar,Bernard; Bruel,Michel; Poumeyrol,Thierry, Method of producing a thin layer of semiconductor material.
  25. Yamagata Kenji (Kawasaki JPX) Yonehara Takao (Atsugi JPX), Method of producing semiconductor substrate.
  26. Yamagata, Kenji, Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device.
  27. Tong,Qin Yi, Method of room temperature covalent bonding.
  28. Hayashi Yoshihiro (Tokyo JPX), Method of stacking semiconductor substrates for fabrication of three-dimensional integrated circuit.
  29. Gonzalez, Fernando, Methods of forming semiconductor constructions.
  30. Gonzalez, Fernando, Methods of forming semiconductor constructions.
  31. Gonzalez, Fernando, Methods of forming semiconductor constructions.
  32. Kusunoki Shigeru (Hyogo JPX), Multi-layer type semiconductor device with semiconductor element layers stacked in opposite direction and manufacturing.
  33. Wahlstrom Sven E. (570 Jackson Dr. Palo Alto CA 94303), Multilevel integrated circuits employing fused oxide layers.
  34. Kiyofumi Sakaguchi JP; Kazutaka Yanagita JP, Porous region removing method and semiconductor substrate manufacturing method.
  35. Curran Patrick A. (Plano TX), Process for making a buried conductor by fusing two wafers.
  36. Takao Yoshihiro (Kawasaki JPX), Process for manufacturing three dimensional IC\s.
  37. Kaga Toru (Saitama JPX) Kawamoto Yoshifumi (Kanagawa JPX) Sunami Hideo (Tokyo JPX), Process for manufacturing vertical dynamic random access memories.
  38. Yamagata Kenji (Kawasaki JPX) Yonehara Takao (Atsugi JPX), Process for producing a semiconductor substrate.
  39. Yamagata Kenji,JPX ; Yonehara Takao,JPX, Process for producing a semiconductor substrate.
  40. Sakaguchi, Kiyofumi; Yonehara, Takao; Nishida, Shoji; Yamagata, Kenji, Process for producing semiconductor article.
  41. Sakaguchi,Kiyofumi; Yonehara,Takao, Process for production of semiconductor substrate.
  42. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  43. Bruel,Michel, Process for the production of thin semiconductor material films.
  44. Kim, Sarah E.; List, R. Scott; Kellar, Scot A., Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices.
  45. Lee, Sang-Yun, Semiconductor bonding and layer transfer method.
  46. Nemati Farid ; Plummer James D., Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches.
  47. Oh, ChoonSik; Lee, Sang-Yun, Semiconductor circuit.
  48. Yoshihara, Shinji; Ohara, Fumio; Nagakubo, Masao, Semiconductor device including eutectic bonding portion and method for manufacturing the same.
  49. Sakaguchi Kiyofumi (Atsugi JPX) Yonehara Takao (Atsugi JPX), Semiconductor device substrate and process for preparing the same.
  50. Lee, Sang-Yun, Semiconductor layer structure and method of making the same.
  51. Lee, Sang-Yun, Semiconductor layer structure and method of making the same.
  52. Lee,Sang Yun, Semiconductor layer structure and method of making the same.
  53. Yonehara Takao (Atsugi JPX), Semiconductor member and process for preparing semiconductor member.
  54. Lee, Sang-Yun, Semiconductor memory device.
  55. Yutaka Akino JP; Tadashi Atoji JP, Semiconductor substrate and method of manufacturing the same.
  56. Akino,Yutaka; Atoji,Tadashi, Semiconductor substrate having a stepped profile.
  57. Ipposhi, Takashi; Matsumoto, Takuji, Semiconductor wafer.
  58. Nemoto, Yoshihiko; Sunohara, Masahiro; Takahashi, Kenji, Semiconductor wafer having a separation portion on a peripheral area.
  59. Atanackovic,Petar B., Semiconductor-on-insulator silicon wafer.
  60. Iyer Subramanian S. ; Baran Emil ; Mastroianni Mark L. ; Craven Robert A., Single-etch stop process for the manufacture of silicon-on-insulator wafers.
  61. Srikrishnan Kris V., Smart-cut process for the production of thin semiconductor material films.
  62. Sugahara Kazuyuki (Hyogo JPX) Ajika Natsuo (Hyogo JPX) Ogawa Toshiaki (Hyogo JPX) Iwamatsu Toshiaki (Hyogo JPX) Ipposhi Takashi (Hyogo JPX), Stacked-type semiconductor device.
  63. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  64. Ito,Masataka; Yamagata,Kenji; Kakizaki,Yasuo; Takanashi,Kazuhito; Miyabayashi,Hiroshi; Moriwaki,Ryuji; Tsuboi,Takashi, Substrate manufacturing method and substrate processing apparatus.
  65. Matsushita Takeshi,JPX, Three-dimensional integrated circuit device and its manufacturing method.
  66. Lee, Sang-Yun, Three-dimensional integrated circuit structure.
  67. Greenlaw, David, Three-dimensional integrated semiconductor devices.
  68. Nemati,Farid; Yang,Kevin J., Thyristor-based memory and its method of operation.
  69. Chu, Jack Oon; Grill, Alfred; Herman, Jr., Dean A.; Saenger, Katherine L., Transferable device-containing layer for silicon-on-insulator applications.
  70. Holloway Thomas C., Variable threshold voltage gate electrode for higher performance mosfets.
  71. Lee,Sang Yun, Vertical memory device structures.
  72. Lee, Sang Yun, Wafer bonding method.
  73. Lee,Sang Yun, Wafer bonding method.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로