|국가/구분||United States(US) Patent 등록|
|국제특허분류(IPC7판)||G06F-003/00 G06F-013/28 G06F-009/30 G06F-009/38 G06F-013/16|
|미국특허분류(USC)||710/004; 710/002; 712/033; 712/201|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 0 인용 특허 : 382|
The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path....
1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising: a functional unit configured to perform a digital operation;one or more multiplexers coupled to the memory bus;a configurable data path configurably coupled to the one or more multiplexers and the functional unit, the configurable data path configured in response to a first configuration information to provide a data path configuration by configuring interconnections between the one or more multiplexers and the ...